Implement generic MAX2771 raw Ethernet recorder

This commit is contained in:
onur
2026-08-01 01:15:47 +03:00
commit 79d07fdda7
57 changed files with 4810 additions and 0 deletions
+27
View File
@@ -0,0 +1,27 @@
`default_nettype none
module reset_sync #(
parameter int unsigned STAGES = 2
) (
input wire logic clk,
input wire logic arst,
output logic srst
);
(* ASYNC_REG = "TRUE" *) logic [STAGES-1:0] sync_ff;
initial begin
if (STAGES < 2) $error("reset_sync STAGES must be at least two");
end
always_ff @(posedge clk or posedge arst) begin
if (arst) begin
sync_ff <= '1;
end else begin
sync_ff <= {sync_ff[STAGES-2:0], 1'b0};
end
end
assign srst = sync_ff[STAGES-1];
endmodule
`default_nettype wire