onur
28 lines
598 B
Systemverilog
28 lines
598 B
Systemverilog
`default_nettype none
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module reset_sync #(
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parameter int unsigned STAGES = 2
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) (
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input wire logic clk,
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input wire logic arst,
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output logic srst
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);
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(* ASYNC_REG = "TRUE" *) logic [STAGES-1:0] sync_ff;
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initial begin
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if (STAGES < 2) $error("reset_sync STAGES must be at least two");
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end
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always_ff @(posedge clk or posedge arst) begin
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if (arst) begin
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sync_ff <= '1;
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end else begin
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sync_ff <= {sync_ff[STAGES-2:0], 1'b0};
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end
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end
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assign srst = sync_ff[STAGES-1];
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endmodule
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`default_nettype wire
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