onur
27 lines
1.2 KiB
Markdown
27 lines
1.2 KiB
Markdown
# Hardware assumptions index
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Board-specific facts and assumptions are kept beside the target that uses them:
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- [Genesys 2 hardware assumptions](../targets/genesys2/docs/hardware_assumptions.md)
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- [Efinix Ti375 C529 hardware assumptions](../targets/efinix_ti375_c529/docs/hardware_assumptions.md)
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The following items are shared assumptions from the recorder specification:
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- the MAX2771 produces one literal 4-bit word on every selected RF clock edge;
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- nominal maximum RF clock frequency is 32.736 MHz;
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- the default capture edge is rising and the default packing puts the earlier
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sample in the high nibble;
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- the source cannot be backpressured.
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The following are deliberately **not** claimed as verified:
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- MAX2771 clock-to-data minimum and maximum delays at the connector;
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- RF cable/adapter clock-to-data skew and signal integrity;
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- a loss-free sample-zero boundary when RF capture starts before Gigabit link;
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- timing behavior outside the FPGA speed/temperature model selected by each
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target build.
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Obtain the MAX2771 timing values from the exact device/mode datasheet and
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measure the assembled clock/data path before final board-level timing sign-off.
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No arbitrary `set_input_delay` is presented as a measured value.
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