onur
34 lines
1008 B
Systemverilog
34 lines
1008 B
Systemverilog
`default_nettype none
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module phy_reset_ctrl #(
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parameter int unsigned CLK_HZ = 125_000_000,
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parameter int unsigned RESET_LOW_MS = 10
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) (
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input wire logic clk,
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input wire logic rst,
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output logic phy_reset_n,
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output logic reset_complete
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);
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localparam longint unsigned RESET_CYCLES = (CLK_HZ / 1000) * RESET_LOW_MS;
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localparam int unsigned COUNT_W = (RESET_CYCLES < 2) ? 1 : $clog2(RESET_CYCLES + 1);
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logic [COUNT_W-1:0] count;
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always_ff @(posedge clk) begin
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if (rst) begin
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phy_reset_n <= 1'b0;
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reset_complete <= 1'b0;
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count <= '0;
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end else if (!reset_complete) begin
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phy_reset_n <= 1'b0;
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if (count == RESET_CYCLES-1) begin
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phy_reset_n <= 1'b1;
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reset_complete <= 1'b1;
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end else count <= count + {{(COUNT_W-1){1'b0}},1'b1};
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end else begin
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phy_reset_n <= 1'b1;
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end
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end
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endmodule
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`default_nettype wire
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