onur
25 lines
1.2 KiB
Markdown
25 lines
1.2 KiB
Markdown
# Timing constraints index
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The authoritative target timing notes are:
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- [Genesys 2 timing constraints](../targets/genesys2/docs/timing_constraints.md)
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- [Efinix timing/build notes](../targets/efinix_ti375_c529/docs/efinity_flow.md)
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Both implementations constrain the RF clock to 30.547 ns by default and the
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Ethernet GMII domain to 8.000 ns. Their generated 125 MHz RGMII transmit clock
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phase and board-specific I/O timing are created in the corresponding target
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clock/periphery implementation.
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Only known asynchronous relationships and synchronizer/Gray-pointer CDC paths
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are treated as asynchronous. The design does not apply a broad false path from
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RF capture to Ethernet logic; the handwritten asynchronous FIFO is the explicit
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boundary. Unknown MAX2771 external input delays remain documented measurement
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requirements rather than invented constraints.
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Clean builds checked on 1 August 2026 reported:
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| Target | Setup slack | Hold slack | CDC |
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|---|---:|---:|---|
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| Genesys 2, Vivado 2026.1 | +0.212 ns worst | +0.090 ns worst | no unexpected major warning accepted by build script |
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| Ti375 C529, Efinity 2026.1 | +0.636 ns Ethernet, +25.614 ns RF | +0.094 ns Ethernet, +0.031 ns RF | no synchronizer warnings |
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