onur
105 lines
3.2 KiB
Markdown
105 lines
3.2 KiB
Markdown
# Digilent Genesys 2 target
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This directory contains only the Genesys 2 adaptation of the MAX2771 recorder.
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The protocol/capture/FIFO/MAC RTL comes from `../../rtl/common`; no portable
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module is copied here.
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## Target-specific files
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| File | Function |
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|---|---|
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| `rtl/max2771_recorder_top.sv` | connects common blocks, status counters and LEDs |
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| `rtl/ethernet_clock_gen_xilinx.sv` | 200 MHz differential input and primitive MMCM for 125 MHz/125 MHz +90° |
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| `rtl/rgmii_tx_xilinx.sv` | Kintex-7 ODDR implementation for TXD/TXCTL/TXC |
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| `rtl/phy_init_rtl8211e.sv` | polls Genesys RTL8211E PHY address 1 and gates 1000/full link |
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| `constraints/genesys2_max2771_recorder.xdc` | verified clock, JA, Ethernet and LED pins |
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| `scripts/build_vivado.tcl` | in-memory/non-project synthesis, P&R, reports and bitstream |
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| `scripts/program_fpga.tcl` | volatile JTAG configuration |
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## Wiring
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| Signal | FPGA ball | JA pin | Standard |
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|---|---:|---:|---|
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| `rf_clk_pmod` | U27 | JA[0] | LVCMOS33 |
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| `rf_data_pmod[0]` | U28 | JA[1] | LVCMOS33 |
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| `rf_data_pmod[1]` | T26 | JA[2] | LVCMOS33 |
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| `rf_data_pmod[2]` | T27 | JA[3] | LVCMOS33 |
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| `rf_data_pmod[3]` | T22 | JA[4] | LVCMOS33 |
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Connect a common ground and use only a 3.3-V-compatible digital source.
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## Simulation
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From the repository root:
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```bash
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make genesys2-sim
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```
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This runs the common FIFO/protocol/MAC regression. Xilinx primitives are
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guarded by `SYNTHESIS`, so vendor simulation libraries are not required for the
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common regression.
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## Build
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```bash
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make genesys2-build
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```
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Equivalent direct command:
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```bash
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vivado -mode batch -source targets/genesys2/scripts/build_vivado.tcl
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```
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Output:
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```text
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build/genesys2/vivado/max2771_recorder.bit
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build/genesys2/reports/
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```
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The build uses part `xc7k325tffg900-2`, top `max2771_recorder_top`, creates an
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in-memory project, fails on negative setup/hold slack or unexpected major CDC
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warnings and uses no block design or generated IP. A clean Vivado 2026.1 build
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on 1 August 2026 completed synthesis, placement, routing, DRC and bitstream
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generation with +0.212 ns worst setup slack and +0.090 ns worst hold slack.
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## Programming
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Connect the Digilent JTAG USB port and run:
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```bash
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make genesys2-program
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```
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This configures the FPGA volatile SRAM. It does not write configuration flash.
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Power cycling removes the design.
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## Clocking and RGMII
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The 200 MHz differential oscillator drives an MMCM with a 1000 MHz VCO. It
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generates 125 MHz at 0° for the MAC/data ODDRs and 125 MHz at +90° for the TXC
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ODDR. The resulting nominal +2 ns clock shift is required because the board
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straps RTL8211E transmit delay off.
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PHY reset remains asserted for 10 ms, register access waits another 30 ms, and
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transmit starts only after PHY-specific status reports resolved 1000 Mb/s/full
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duplex link. Ethernet receive is not implemented.
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## LEDs
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| LED | Meaning |
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| 0 | MMCM locked/system ready |
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| 1 | qualified 1000/full link |
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| 2 | RF sample activity |
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| 3 | FIFO non-empty |
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| 4 | sample loss/overflow latched |
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| 5 | frame activity |
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| 6 | first PHY status read completed |
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| 7 | Ethernet-domain heartbeat |
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See [hardware assumptions](docs/hardware_assumptions.md) and
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[timing constraints](docs/timing_constraints.md) before hardware sign-off.
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