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Add the missing TPS2121 status pull-up (R108) and correct the power-mux docs

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The power mux's status output had no pull-up, which broke the USB current
budget interlock.

TPS2121 ST is an open-drain output; the datasheet lists RST = 6-20 kOhm under
Recommended Operating Conditions, alongside RILM, so it is an external part.
ST is driven low only while IN2 (the J3 external 5 V header) is sourcing OUT,
and is high impedance whenever IN1 (the J7 USB-C input) is sourcing. U10 gate 2
inverts MUX_ST into EXT_SELECTED, and MAIN_EN = USB_3A_OK OR EXT_SELECTED
enables the 15 A core buck. With MUX_ST floating on USB-C power, a drift low
asserts MAIN_EN no matter what the TUSB320 advertised, so the board would try
to bring up the core rail on a 500 mA port. Every other open-drain net here
already has its pull-up (R7/R8, R30, R33/R34, R98/R104/R105/R106); this one was
missed.

R108 (10 k, VCC3V3_AUX -> MUX_ST) is appended at the end of design_data.py
rather than beside the mux: reference designators are assigned in call order,
so inserting it mid-file would renumber every later resistor and invalidate the
routed board. Placed at (53.0, 101.6), 2.4 mm from the U10 gate it holds up,
on a site checked clear of existing copper, and routed with close_remaining.py.

Also corrects POWER_TREE.md, which credited PR1 for giving the external input
priority. PR1 = GND actually *disables* priority mode; CP2 (tied to VCC3V3_AUX)
is what selects IN2. Since CP2 derives from the mux's own output the behaviour
is two-phase - highest-voltage wins at cold start, IN2 unconditionally once the
aux rail is up - so with both inputs connected there can be one seamless
switchover at startup. Documented, with the numbers: both eFuses UV 3.98 V /
OV 5.80 V, ILIM 2.69 A (USB-C) and 4.04 A (header), mux OV 5.69 V / ILIM 4.5 A.
The two inputs are never summed: both eFuses block reverse current and the mux
bonds exactly one input at a time.

board_routed.kicad_sch/.kicad_sym are now gitignored byte copies of the tracked
schematic; kicad-cli needs them beside the board for --schematic-parity, and
deleting them in the previous commit had silently disabled that check.

Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group,
schematic parity unchanged at the 402 pre-existing warnings.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
This commit is contained in:
onur
2026-09-01 12:28:00 +03:00
parent 95609a6b6a
commit 1ea2bc64ac
15 changed files with 3838 additions and 2710 deletions
Download Patch File Download Diff File Expand all files Collapse all files
outputs/bom.csv
+2 -1
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@@ -101,6 +101,7 @@ R103,1,1K,Yageo,RC0402FR-071KL,Resistor_SMD:R_0402_1005Metric,SMT,no,External-re
R104,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,LM3880 final-flag pull-up for all-power logic
R105,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,1.8-V power-good pull-up for all-power logic
R106,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,3.3-V power-good pull-up for all-power logic
R108,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,"TPS2121 open-drain status pull-up (RST, 6-20 kohm)"
"R11,R16",2,232K,Yageo,RC0402FR-07232KL,Resistor_SMD:R_0402_1005Metric,SMT,no,4.0-V nominal eFuse UV divider top
"R12,R17",2,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse UV divider bottom
"R13,R18",2,383K,Yageo,RC0402FR-07383KL,Resistor_SMD:R_0402_1005Metric,SMT,no,5.8-V nominal eFuse OV divider top
@@ -209,4 +210,4 @@ U35,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-
U5,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,SMT,no,USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2; current-advertisement outputs unused since this port never sources SYS5
U6,1,TPD2EUSB30A,Texas Instruments,TPD2EUSB30ADRTR,Package_TO_SOT_SMD:Texas_DRT-3,SMT,no,Low-capacitance USB 2.0 ESD protection
"U7,U8",2,TPS259470A,Texas Instruments,TPS259470ARPWR,board:Texas_RPW0010A_QFN10,SMT,no,True-reverse-blocking eFuse; UV/OV/current/inrush protection
U9,1,TPS2121,Texas Instruments,TPS2121RUXR,board:Texas_RUX0012A_VQFN12,SMT,no,4.5-A power mux; external input wins near-equal valid 5-V inputs
U9,1,TPS2121,Texas Instruments,TPS2121RUXR,board:Texas_RUX0012A_VQFN12,SMT,no,4.5-A power mux. PR1=GND disables priority mode; CP2 tied to VCC3V3_AUX is what selects IN2 (external 5 V) once the aux rail is up
1 Reference Qty Value Manufacturer MPN Footprint Assembly DNP Description
101 R104 1 10K Yageo RC0402FR-0710KL Resistor_SMD:R_0402_1005Metric SMT no LM3880 final-flag pull-up for all-power logic
102 R105 1 10K Yageo RC0402FR-0710KL Resistor_SMD:R_0402_1005Metric SMT no 1.8-V power-good pull-up for all-power logic
103 R106 1 10K Yageo RC0402FR-0710KL Resistor_SMD:R_0402_1005Metric SMT no 3.3-V power-good pull-up for all-power logic
104 R108 1 10K Yageo RC0402FR-0710KL Resistor_SMD:R_0402_1005Metric SMT no TPS2121 open-drain status pull-up (RST, 6-20 kohm)
105 R11,R16 2 232K Yageo RC0402FR-07232KL Resistor_SMD:R_0402_1005Metric SMT no 4.0-V nominal eFuse UV divider top
106 R12,R17 2 100K Yageo RC0402FR-07100KL Resistor_SMD:R_0402_1005Metric SMT no eFuse UV divider bottom
107 R13,R18 2 383K Yageo RC0402FR-07383KL Resistor_SMD:R_0402_1005Metric SMT no 5.8-V nominal eFuse OV divider top
210 U5 1 TUSB320LAI Texas Instruments TUSB320LAIRSW(R) Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm SMT no USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2; current-advertisement outputs unused since this port never sources SYS5
211 U6 1 TPD2EUSB30A Texas Instruments TPD2EUSB30ADRTR Package_TO_SOT_SMD:Texas_DRT-3 SMT no Low-capacitance USB 2.0 ESD protection
212 U7,U8 2 TPS259470A Texas Instruments TPS259470ARPWR board:Texas_RPW0010A_QFN10 SMT no True-reverse-blocking eFuse; UV/OV/current/inrush protection
213 U9 1 TPS2121 Texas Instruments TPS2121RUXR board:Texas_RUX0012A_VQFN12 SMT no 4.5-A power mux; external input wins near-equal valid 5-V inputs 4.5-A power mux. PR1=GND disables priority mode; CP2 tied to VCC3V3_AUX is what selects IN2 (external 5 V) once the aux rail is up
outputs/drc_final_routed.rpt
+1208 -2
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File diff suppressed because it is too large Load Diff
outputs/erc_final_reset.rpt
+1 -1
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@@ -1,4 +1,4 @@
ERC report (2026-08-21T00:59:47, Encoding UTF8)
ERC report (2026-09-01T12:27:27, Encoding UTF8)
Report includes: Errors, Warnings, Exclusions
***** Sheet /
outputs/jlcpcb_bom.csv
+1
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@@ -101,6 +101,7 @@ MMBT3904,Q1,Package_TO_SOT_SMD:SOT-23,,onsemi,MMBT3904LT1G,1,SMT,no
10K,R104,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
10K,R105,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
10K,R106,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
10K,R108,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
232K,"R11,R16",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07232KL,2,SMT,no
100K,"R12,R17",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,2,SMT,no
383K,"R13,R18",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07383KL,2,SMT,no
1 Comment Designator Footprint LCSC Part # Manufacturer Manufacturer Part Number Quantity Assembly Type DNP
101 10K R104 Resistor_SMD:R_0402_1005Metric Yageo RC0402FR-0710KL 1 SMT no
102 10K R105 Resistor_SMD:R_0402_1005Metric Yageo RC0402FR-0710KL 1 SMT no
103 10K R106 Resistor_SMD:R_0402_1005Metric Yageo RC0402FR-0710KL 1 SMT no
104 10K R108 Resistor_SMD:R_0402_1005Metric Yageo RC0402FR-0710KL 1 SMT no
105 232K R11,R16 Resistor_SMD:R_0402_1005Metric Yageo RC0402FR-07232KL 2 SMT no
106 100K R12,R17 Resistor_SMD:R_0402_1005Metric Yageo RC0402FR-07100KL 2 SMT no
107 383K R13,R18 Resistor_SMD:R_0402_1005Metric Yageo RC0402FR-07383KL 2 SMT no
outputs/routing_report.txt
+5 -5
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@@ -1,10 +1,10 @@
Board: hardware/board_routed.kicad_pcb
Unconnected endpoints reported by connectivity: 0
Tracks: 3065 Vias: 1018
Tracks: 3068 Vias: 1020
Track segments per layer:
F.Cu 1746
L6_SIG 481
F.Cu 1748
L6_SIG 482
L5_SIG 390
L3_SIG 387
B.Cu 61
@@ -12,8 +12,8 @@ Track segments per layer:
Track width used per net class (mm: segments):
BGA_ESCAPE 0.1: 423
CLOCK 0.1: 17, 0.15: 145
Default 0.1: 37, 0.12: 1373, 0.15: 5
POWER 0.1: 79, 0.12: 4, 0.15: 193, 0.163: 18, 0.195: 1, 0.2: 4, 0.22: 12, 0.227: 3, 0.25: 247, 0.26: 6, 0.3: 327, 0.35: 1, 0.4: 103, 0.45: 2, 0.5: 2, 0.55: 10, 0.6: 4, 0.7: 2, 0.8: 5, 1.0: 1, 1.2: 4, 1.5: 2
Default 0.1: 37, 0.12: 1375, 0.15: 5
POWER 0.1: 79, 0.12: 4, 0.15: 193, 0.163: 18, 0.195: 1, 0.2: 4, 0.22: 12, 0.227: 3, 0.25: 248, 0.26: 6, 0.3: 327, 0.35: 1, 0.4: 103, 0.45: 2, 0.5: 2, 0.55: 10, 0.6: 4, 0.7: 2, 0.8: 5, 1.0: 1, 1.2: 4, 1.5: 2
RF50_CPWG 0.164: 11
USB90_DIFF 0.135: 24