Fix the RF launch: relieve the planes under J2 and put the ESD on the line

The 0.164/0.200 CPWG geometry was fine; the calculation just stopped at the
trace and never covered the connector launch, which is where the real
discontinuity was.

J2's centre land is 1.5 mm wide because that is what the connector's centre pin
needs mechanically. Sitting on solid L2_GND only 0.0994 mm below, that land is
a 10.7 ohm transmission line, not a 50 ohm one. The 1.84 mm of it over the
plane is 6.7 degrees at L1 and reflects 12 dB (VSWR 1.67) - by far the worst
discontinuity in the chain, and worse than everything the carefully built
0.164 mm line downstream avoids.

RF_LAUNCH_RELIEF voids L2_GND and L3_SIG under the land, (172.35, 40.95) to
(175.10, 43.05). The reference drops to L4_PWR - VCC3V0_RF, an AC ground -
0.587 mm below, which raises the launch to 37 ohm and 30 dB. L3 carried no
pour and no copper there, so only L2 actually had to go; the area covers L3 as
well so a later edit cannot fill the gap back in. It stops where the land ends
and the 0.164 mm line begins, verified: L2 GND is absent across the whole land
and present again at x = 172.0 and inboard.

D1's ESD clamp sat at the end of a 1.34 mm spur, where its 0.3 pF presented
-j228 ohm and cost 3.4 dB for nothing. D1 is rotated onto the run at
(171.30, 42.416) so pad 1 overlaps the line directly and pad 2 lands in the
RF ground pour; the spur is deleted.

Return loss, worst term first:
  SMA launch land      12.0 -> 30.0 dB   (10.7 -> 37.0 ohm)
  D1 ESD clamp         19.2 -> 22.6 dB   (now just the part's own 0.3 pF)
  C85 DNP tuning stub  25.5 dB unchanged, intentional provision
  C84 DNP land in line 30.1 dB unchanged, negligible
  worst-case coherent   7.0 -> 14.4 dB
The dominant term is now a component choice rather than a layout defect.

Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group,
parity unchanged at the 402 pre-existing warnings, RF still 10 segments all on
F.Cu at exactly 0.164 mm.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
This commit is contained in:
onur
2026-09-01 12:55:49 +03:00
parent 1ea2bc64ac
commit 4fa38e35bd
6 changed files with 781 additions and 712 deletions
+11 -1
View File
@@ -85,7 +85,17 @@ yoktur.
## RF ve yüksek hızlı routing kuralları ## RF ve yüksek hızlı routing kuralları
- RF katı üst katmanda, JLC08161H-3313 stackup için 0.164 mm genişlik ve - RF katı üst katmanda, JLC08161H-3313 stackup için 0.164 mm genişlik ve
0.200 mm coplanar GND aralığıyla 50 ohm CPWG olarak tasarlanır. 0.200 mm coplanar GND aralığıyla 50 ohm CPWG olarak tasarlanır. Kontrollü
empedans siparişinde bu geometri üreticinin kendi hesabıyla doğrulanmalıdır.
- J2 edge-launch pad'inin altında `RF_LAUNCH_RELIEF` ile L2/L3 boşaltılır.
Konnektörün 1.5 mm genişliğindeki merkez pad'i, 0.0994 mm altındaki dolu
L2_GND üzerinde 50 ohm değil **10.7 ohm**'luk bir hat parçasıdır; plane
boşaltılmadan bu launch tek başına 12 dB return loss ile bütün RF yolunun en
kötü süreksizliğidir. Referans L4_PWR'a (VCC3V0_RF, AC ground) inince launch
~37 ohm ve ~30 dB olur. Boşaltma x=172.35'te, pad bitip 0.164 mm hat
başladığı yerde durur; hat kendi L2 referansını korur.
- D1 ESD klemp doğrudan hattın üzerindedir. 1.34 mm'lik bir stub ucunda
0.3 pF, L1'de -j228 ohm görünüp 3.4 dB return loss'a mal oluyordu.
- SMA, ESD, bias-tee, SAW ve MAX2771 MIXIN_HI arasındaki RF güzergâhında dijital - SMA, ESD, bias-tee, SAW ve MAX2771 MIXIN_HI arasındaki RF güzergâhında dijital
route veya via kullanılmaz. route veya via kullanılmaz.
- USB2 diferansiyel çift 0.135 mm hat ve 0.150 mm coupled gap kuralındadır. - USB2 diferansiyel çift 0.135 mm hat ve 0.150 mm coupled gap kuralındadır.
File diff suppressed because it is too large Load Diff
+2 -2
View File
@@ -1,5 +1,5 @@
** Drc report for board_routed.kicad_pcb ** ** Drc report for board_routed.kicad_pcb **
** Created on 2026-09-01T12:27:30 ** ** Created on 2026-09-01T12:55:21 **
** Report includes: Errors, Warnings, Exclusions ** ** Report includes: Errors, Warnings, Exclusions **
** Found 0 DRC violations ** ** Found 0 DRC violations **
@@ -402,7 +402,7 @@
@(32.7851 mm, 28.2169 mm): Footprint C129 @(32.7851 mm, 28.2169 mm): Footprint C129
[footprint_symbol_mismatch]: Texas_DPY0002A_X1SON doesn't match footprint given by symbol (board:Texas_DPY0002A_X1SON) [footprint_symbol_mismatch]: Texas_DPY0002A_X1SON doesn't match footprint given by symbol (board:Texas_DPY0002A_X1SON)
Local override; warning Local override; warning
@(170.4500 mm, 40.7500 mm): Footprint D1 @(171.3000 mm, 42.4159 mm): Footprint D1
[footprint_symbol_mismatch]: D_SOD-523 doesn't match footprint given by symbol (Diode_SMD:D_SOD-523) [footprint_symbol_mismatch]: D_SOD-523 doesn't match footprint given by symbol (Diode_SMD:D_SOD-523)
Local override; warning Local override; warning
@(78.0000 mm, 100.5000 mm): Footprint D2 @(78.0000 mm, 100.5000 mm): Footprint D2
+3 -3
View File
@@ -1,9 +1,9 @@
Board: hardware/board_routed.kicad_pcb Board: hardware/board_routed.kicad_pcb
Unconnected endpoints reported by connectivity: 0 Unconnected endpoints reported by connectivity: 0
Tracks: 3068 Vias: 1020 Tracks: 3067 Vias: 1020
Track segments per layer: Track segments per layer:
F.Cu 1748 F.Cu 1747
L6_SIG 482 L6_SIG 482
L5_SIG 390 L5_SIG 390
L3_SIG 387 L3_SIG 387
@@ -14,7 +14,7 @@ Track width used per net class (mm: segments):
CLOCK 0.1: 17, 0.15: 145 CLOCK 0.1: 17, 0.15: 145
Default 0.1: 37, 0.12: 1375, 0.15: 5 Default 0.1: 37, 0.12: 1375, 0.15: 5
POWER 0.1: 79, 0.12: 4, 0.15: 193, 0.163: 18, 0.195: 1, 0.2: 4, 0.22: 12, 0.227: 3, 0.25: 248, 0.26: 6, 0.3: 327, 0.35: 1, 0.4: 103, 0.45: 2, 0.5: 2, 0.55: 10, 0.6: 4, 0.7: 2, 0.8: 5, 1.0: 1, 1.2: 4, 1.5: 2 POWER 0.1: 79, 0.12: 4, 0.15: 193, 0.163: 18, 0.195: 1, 0.2: 4, 0.22: 12, 0.227: 3, 0.25: 248, 0.26: 6, 0.3: 327, 0.35: 1, 0.4: 103, 0.45: 2, 0.5: 2, 0.55: 10, 0.6: 4, 0.7: 2, 0.8: 5, 1.0: 1, 1.2: 4, 1.5: 2
RF50_CPWG 0.164: 11 RF50_CPWG 0.164: 10
USB90_DIFF 0.135: 24 USB90_DIFF 0.135: 24
Nets still split into more than one copper group: Nets still split into more than one copper group:
+40 -2
View File
@@ -141,8 +141,9 @@ def route_rf(board: pcbnew.BOARD) -> None:
dc_block_1 = pad_xy(board, "C83", "1") dc_block_1 = pad_xy(board, "C83", "1")
l4_2 = pad_xy(board, "L4", "2") l4_2 = pad_xy(board, "L4", "2")
add_polyline(board, "RF_SMA", [j2_inner, (170.10, 42.09), l4_2, dc_block_1], w) add_polyline(board, "RF_SMA", [j2_inner, (170.10, 42.09), l4_2, dc_block_1], w)
d1 = pad_xy(board, "D1", "1") # D1 sits directly on the 50-ohm line: its pad 1 overlaps the run above,
add_polyline(board, "RF_SMA", [d1, (d1[0], 42.09)], w) # so no spur is drawn. On a 1.34-mm stub the 0.3-pF clamp presented
# -j228 ohm at L1 and cost 3.4 dB of return loss for nothing.
add_polyline(board, "RF_PRE_SAW", add_polyline(board, "RF_PRE_SAW",
[pad_xy(board, "C83", "2"), pad_xy(board, "FL1", "1")], w) [pad_xy(board, "C83", "2"), pad_xy(board, "FL1", "1")], w)
@@ -433,6 +434,42 @@ def add_named_rule_areas(board: pcbnew.BOARD) -> None:
board.Add(area) board.Add(area)
def add_rf_launch_relief(board: pcbnew.BOARD) -> None:
"""Void the reference planes under the SMA edge-launch pad.
J2's centre land is 1.5 mm wide because that is what the connector's
centre pin needs mechanically, but 1.5 mm of copper 0.0994 mm above a
solid L2_GND is a 10.7-ohm transmission line, not a 50-ohm one. The
1.84 mm of it that sits over the plane is 6.7 degrees long at L1 and
reflects 12 dB - by far the worst discontinuity in the RF path, and worse
than everything the 0.164-mm line downstream is carefully built to avoid.
Removing the plane under the land moves its reference down to L4_PWR
(VCC3V0_RF, an AC ground) 0.587 mm below, which raises the launch to about
37 ohms and 30 dB. L3_SIG carries no pour and no copper here, so this
only has to void L2; the area covers L3 as well so a later edit cannot
fill the gap back in. It stops at x = 172.35, where the land ends and the
0.164-mm line begins, so the line keeps its own L2 reference.
"""
relief = pcbnew.LSET()
for layer in (pcbnew.In1_Cu, pcbnew.In2_Cu): # L2_GND, L3_SIG
relief.AddLayer(layer)
area = pcbnew.ZONE(board)
area.SetZoneName("RF_LAUNCH_RELIEF")
area.SetIsRuleArea(True)
area.SetLayerSet(relief)
area.SetDoNotAllowTracks(True)
area.SetDoNotAllowVias(True)
area.SetDoNotAllowZoneFills(True)
area.SetDoNotAllowPads(False)
area.SetDoNotAllowFootprints(False)
outline = area.Outline()
outline.NewOutline()
for x, y in ((172.35, 40.95), (175.10, 40.95), (175.10, 43.05), (172.35, 43.05)):
outline.Append(point(x, y))
board.Add(area)
def routed_lengths(board: pcbnew.BOARD) -> dict[str, float]: def routed_lengths(board: pcbnew.BOARD) -> dict[str, float]:
totals = {net: 0.0 for net in CRITICAL_NETS} totals = {net: 0.0 for net in CRITICAL_NETS}
for item in board.GetTracks(): for item in board.GetTracks():
@@ -473,6 +510,7 @@ def main() -> None:
route_rf(board) route_rf(board)
route_usb(board) route_usb(board)
add_rf_ground(board) add_rf_ground(board)
add_rf_launch_relief(board)
add_named_rule_areas(board) add_named_rule_areas(board)
# The reserved RF and USB corridors are gone now, so the power pads that # The reserved RF and USB corridors are gone now, so the power pads that
+1 -1
View File
@@ -92,7 +92,7 @@ MAJOR = {
"U33": (87, 103, 0), "U33": (87, 103, 0),
# RF front end. J2's launch reference is exactly on the right PCB edge. # RF front end. J2's launch reference is exactly on the right PCB edge.
"J2": (175, 42, 0), "D1": (170.45, 40.75, 0), "FL1": (164.0, 42.1, 180), "J2": (175, 42, 0), "D1": (171.30, 41.715, 270), "FL1": (164.0, 42.1, 180),
"J5": (171, 56, 0), "U27": (165, 52, 0), "U21": (155.5, 45, 0), "J5": (171, 56, 0), "U27": (165, 52, 0), "U21": (155.5, 45, 0),
"U23": (149, 53, 0), "U24": (137, 55, 0), "U23": (149, 53, 0), "U24": (137, 55, 0),
} }