Complete the routing: 0 DRC violations, 0 unconnected

The board now routes end to end. Every net carrying two or more pads is a
single connected copper group (216 nets, 1175 pads); kicad-cli reports 0 DRC
violations and 0 unconnected items with zones refilled.

Freerouting was never the blocker. The 14 remaining opens were three separate
defects:

1. Obstacles in route_local_power.py modelled every pad as its axis-aligned
   bounding box. A 0.8-mm BGA dogbone site sits diagonally between four lands:
   true clearance 0.1407 mm, but the box test measured 0.4 mm from the box edge
   and rejected it, so no via could be placed anywhere in the Ti375 escape
   field. Replaced with an exact rounded-rectangle model, validated against
   KiCad's own SHAPE::Collide to 0.00 um over 14850 samples. Same 0 DRC and one
   fewer unconnected at the route_local_power stage.

2. CLOCK's 0.15-mm clearance cannot physically escape the BGA: two adjacent
   0.45-mm dogbone vias on 0.8-mm pitch leave a 0.35-mm channel and a 0.10-mm
   trace needs 0.40 mm. HARD_TCK and MAX_SCLK could never leave the package.
   New rule "Ti375 escape field copper clearance" relaxes clearance to the
   0.10 mm this field already uses, only where both objects are inside U1's
   courtyard. The clock trunk keeps 0.15 mm outside it.

3. RF_NO_DIGITAL was a rectangle reaching 7 mm past the RF line, covering the
   MAX2771's whole digital pin field and forcing every U21 output onto F.Cu
   alone. Narrowed to the corridor generate_pcb.py already reserves as
   TEMP_RF_LINE (y <= 43.7), clearing RF copper by 1.1 mm. The RF return path
   is guaranteed by the unrouted L2/L7 ground planes, not by this area.

scripts/close_remaining.py replaces the ad-hoc residual scripts: a multi-layer
maze over (x, y, layer) at 0.1 mm on all five routable layers, seeded from all
copper of both groups, exact clearances, 0.10-mm necking inside the escape
field, and reversible rip-up that rolls back entirely if a displaced net cannot
be put back. ~150 s for the whole board.

Also removes the regenerable intermediate boards, one-off session logs and the
superseded residual scripts, and tracks board_routed.* as the deliverable.

The 402 schematic-parity warnings are pre-existing and unchanged: 199
auto-named unconnected pins, 199 footprint library-nickname mismatches, and 4
mounting holes with no symbol. None affects connectivity or fabrication.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d

hardware/board-cache.lib

@@ -5100,4 +5100,85 @@ X A 2 700 0 200 L 30 30 1 1 P
 ENDDRAW
 ENDDEF
 #
+# BOARD_J7
+#
+DEF BOARD_J7 J 0 30 Y Y 1 L N
+F0 "J7" 0 200 50 H V C CNN
+F1 "USB-C power input" 0 100 50 H V C CNN
+F2 "Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal" 0 -100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -500 500 500 -500 1 1 10 f
+X GND A1 -700 400 200 R 30 30 1 1 P
+X VBUS A4 700 350 200 L 30 30 1 1 P
+X CC1 A5 -700 300 200 R 30 30 1 1 P
+X D A6 700 250 200 L 30 30 1 1 P
+X D A7 -700 200 200 R 30 30 1 1 P
+X SBU1 A8 700 150 200 L 30 30 1 1 P
+X VBUS A9 -700 100 200 R 30 30 1 1 P
+X GND A12 700 50 200 L 30 30 1 1 P
+X GND B1 -700 0 200 R 30 30 1 1 P
+X VBUS B4 700 -50 200 L 30 30 1 1 P
+X CC2 B5 -700 -100 200 R 30 30 1 1 P
+X D B6 700 -150 200 L 30 30 1 1 P
+X D B7 -700 -200 200 R 30 30 1 1 P
+X SBU2 B8 700 -250 200 L 30 30 1 1 P
+X VBUS B9 -700 -300 200 R 30 30 1 1 P
+X GND B12 700 -350 200 L 30 30 1 1 P
+X SHIELD SH -700 -400 200 R 30 30 1 1 P
+ENDDRAW
+ENDDEF
+#
+# BOARD_U35
+#
+DEF BOARD_U35 U 0 30 Y Y 1 L N
+F0 "U35" 0 200 50 H V C CNN
+F1 "TUSB320LAI" 0 100 50 H V C CNN
+F2 "Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm" 0 -100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -500 350 500 -350 1 1 10 f
+X CC1 1 -700 250 200 R 30 30 1 1 B
+X CC2 2 700 250 200 L 30 30 1 1 B
+X PORT 3 -700 150 200 R 30 30 1 1 I
+X VBUS_DET 4 700 150 200 L 30 30 1 1 I
+X ADDR 5 -700 50 200 R 30 30 1 1 P
+X OUT3 6 700 50 200 L 30 30 1 1 O
+X OUT1 7 -700 -50 200 R 30 30 1 1 O
+X OUT2 8 700 -50 200 L 30 30 1 1 O
+X ID 9 -700 -150 200 R 30 30 1 1 O
+X GND 10 700 -150 200 L 30 30 1 1 W
+X EN_N 11 -700 -250 200 R 30 30 1 1 I
+X VDD 12 700 -250 200 L 30 30 1 1 W
+ENDDRAW
+ENDDEF
+#
+# BOARD_R107
+#
+DEF BOARD_R107 R 0 30 Y Y 1 L N
+F0 "R107" 0 200 50 H V C CNN
+F1 "900K" 0 100 50 H V C CNN
+F2 "Resistor_SMD:R_0402_1005Metric" 0 -100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -500 150 500 -150 1 1 10 f
+X 1 1 -700 0 200 R 30 30 1 1 P
+X 2 2 700 0 200 L 30 30 1 1 P
+ENDDRAW
+ENDDEF
+#
+# BOARD_C129
+#
+DEF BOARD_C129 C 0 30 Y Y 1 L N
+F0 "C129" 0 200 50 H V C CNN
+F1 "100nF" 0 100 50 H V C CNN
+F2 "Capacitor_SMD:C_0402_1005Metric" 0 -100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -500 150 500 -150 1 1 10 f
+X 1 1 -700 0 200 R 30 30 1 1 P
+X 2 2 700 0 200 L 30 30 1 1 P
+ENDDRAW
+ENDDEF
+#
 #End Library