Complete the routing: 0 DRC violations, 0 unconnected
The board now routes end to end. Every net carrying two or more pads is a single connected copper group (216 nets, 1175 pads); kicad-cli reports 0 DRC violations and 0 unconnected items with zones refilled. Freerouting was never the blocker. The 14 remaining opens were three separate defects: 1. Obstacles in route_local_power.py modelled every pad as its axis-aligned bounding box. A 0.8-mm BGA dogbone site sits diagonally between four lands: true clearance 0.1407 mm, but the box test measured 0.4 mm from the box edge and rejected it, so no via could be placed anywhere in the Ti375 escape field. Replaced with an exact rounded-rectangle model, validated against KiCad's own SHAPE::Collide to 0.00 um over 14850 samples. Same 0 DRC and one fewer unconnected at the route_local_power stage. 2. CLOCK's 0.15-mm clearance cannot physically escape the BGA: two adjacent 0.45-mm dogbone vias on 0.8-mm pitch leave a 0.35-mm channel and a 0.10-mm trace needs 0.40 mm. HARD_TCK and MAX_SCLK could never leave the package. New rule "Ti375 escape field copper clearance" relaxes clearance to the 0.10 mm this field already uses, only where both objects are inside U1's courtyard. The clock trunk keeps 0.15 mm outside it. 3. RF_NO_DIGITAL was a rectangle reaching 7 mm past the RF line, covering the MAX2771's whole digital pin field and forcing every U21 output onto F.Cu alone. Narrowed to the corridor generate_pcb.py already reserves as TEMP_RF_LINE (y <= 43.7), clearing RF copper by 1.1 mm. The RF return path is guaranteed by the unrouted L2/L7 ground planes, not by this area. scripts/close_remaining.py replaces the ad-hoc residual scripts: a multi-layer maze over (x, y, layer) at 0.1 mm on all five routable layers, seeded from all copper of both groups, exact clearances, 0.10-mm necking inside the escape field, and reversible rip-up that rolls back entirely if a displaced net cannot be put back. ~150 s for the whole board. Also removes the regenerable intermediate boards, one-off session logs and the superseded residual scripts, and tracks board_routed.* as the deliverable. The 402 schematic-parity warnings are pre-existing and unchanged: 199 auto-named unconnected pins, 199 footprint library-nickname mismatches, and 4 mounting holes with no symbol. None affects connectivity or fabrication. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
This commit is contained in:
onur
+3
-2
@@ -14,12 +14,12 @@ __pycache__/
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# Local manufacturer documents; links and policy are in references/README.md
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references/official/
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# Stale/intermediate routed board variants
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# Stale/intermediate routed board variants, regenerated by the routing flow.
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# board_routed.* is the finished deliverable and IS tracked.
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hardware/board_prerouted.*
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hardware/board_plane_stitched.*
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hardware/board_power_routed.*
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hardware/board_power_local.*
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hardware/board_routed.*
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# KiCad writes these when it rescues a symbol; the originals are tracked.
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hardware/rescue-backup/
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@@ -33,3 +33,4 @@ outputs/*
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!outputs/drc_final_placement.rpt
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!outputs/drc_final_routed.rpt
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!outputs/board_final_reset_top.png
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!outputs/routing_report.txt
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+12
-4
@@ -147,11 +147,19 @@ tarafında 10 kohm idle pull-up vardır.
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## USB-C güç ve veri
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- J1 CC1/CC2 -> U5 TUSB320LAI; PORT=GND ile UFP/sink.
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Üç konnektör birbirinden bağımsızdır: `J7` yalnızca USB-C güç girişi, `J3`
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yalnızca harici 5 V güç girişi, `J1` ise yalnızca JTAG/UART debug portudur.
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J1 hiçbir zaman SYS5'i beslemez; bu yüzden J1'e bağlı bir host, kartın 5 V
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gücüne back-feed edemez.
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- J1 CC1/CC2 -> U5 TUSB320LAI; PORT=GND ile UFP/sink; OUT1/OUT2 kullanılmıyor.
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- J1 D+/D− -> U6 TPD2EUSB30A -> R63/R64 27 ohm -> U2 FT4232H.
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- J1 VBUS -> U7 TPS259470A -> `USB5_PROT` -> U9 TPS2121 -> `SYS5`.
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- J1 VBUS -> yalnızca yerel algılama: 900 kohm bölücüyle U5 `VBUS_DET`,
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4.7 k/10 k bölücüyle self-powered FT4232H `RESET_N`.
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- J7 CC1/CC2 -> U35 TUSB320LAI; PORT=GND ile UFP/sink.
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- J7 VBUS -> U7 TPS259470A -> `USB5_PROT` -> U9 TPS2121 -> `SYS5`.
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- Harici J3 5 V -> U8 TPS259470A -> `EXT5_PROT` -> U9 TPS2121 -> `SYS5`.
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- U10/U11, USB 3 A ilanı veya seçilmiş harici kaynak yoksa ana FPGA güç
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- U10/U11, J7 3 A ilanı veya seçilmiş harici kaynak yoksa ana FPGA güç
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converterlarını kapalı tutar.
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## Test noktaları
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@@ -161,7 +169,7 @@ tarafında 10 kohm idle pull-up vardır.
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| TP1 | `U7_FLT` | USB eFuse fault |
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| TP2 | `U8_FLT` | Harici giriş eFuse fault |
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| TP3 | `ANT_BIAS_OC` | Aktif anten over-current |
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| TP4 | `VBUS_RAW` | USB VBUS |
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| TP4 | `VBUS_RAW` | J7 USB-C güç girişi VBUS'ı |
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| TP5 | `EXT5_RAW` | Harici 5 V giriş |
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| TP6 | `SYS5` | Seçilmiş sistem 5 V |
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| TP7 | `VCC3V3_AUX` | Her zaman açık yardımcı 3.3 V |
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+24
-5
@@ -2,21 +2,40 @@
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## Giriş yolu
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Kartta üç ayrı USB-C/güç konnektörü vardır ve hiçbiri birden fazla rolü
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paylaşmaz: `J7` yalnızca USB-C güç girişidir, `J3` yalnızca harici 5 V güç
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girişidir, `J1` ise yalnızca JTAG/UART debug portudur ve SYS5'i hiçbir zaman
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beslemez.
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```text
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USB-C VBUS -> U7 TPS259470A (2.69 A typ) -> USB5_PROT --+
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J7 USB-C VBUS -> U7 TPS259470A (2.69 A typ) -> USB5_PROT --+
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+-> U9 TPS2121 -> SYS5
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EXT_5V ----> U8 TPS259470A (4.04 A typ) -> EXT5_PROT --+
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J3 EXT_5V ----> U8 TPS259470A (4.04 A typ) -> EXT5_PROT --+
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J1 USB-C VBUS -> yalnızca yerel algılama (U5 VBUS_DET, FTDI_RESET_N bölücüsü);
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SYS5'e veya herhangi bir eFuse'a bağlı değil.
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```
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Her iki eFuse yaklaşık 4.0 V UV ve 5.8 V OV eşiğine, kontrollü output slew'a,
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fault test noktasına ve true reverse-current blocking'e sahiptir. U9 4.5 A
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limitli power mux'tur; yakın geçerli girişlerde harici 5 V yolu önceliklidir.
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Böylece J7 ve J3 aynı anda bağlı olsa bile SYS5 her zaman tek bir kaynaktan
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beslenir, ikisi asla toplanmaz.
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USB yolunda TUSB320 CC ilanı U10 tarafından decode edilir. `MAIN_EN`, yalnızca
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USB kaynağı 3 A ilan ettiğinde veya harici giriş gerçekten U9 tarafından
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seçildiğinde yükselir. `VCC3V3_AUX` ise U12 üzerinden SYS5 var olduğu sürece
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USB güç yolunda TUSB320 (U35, J7 üzerinde) CC ilanını decode eder ve
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`TUSB_OUT1`/`TUSB_OUT2` üzerinden U10'a bildirir. `MAIN_EN`, yalnızca J7 3 A
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ilan ettiğinde veya harici giriş gerçekten U9 tarafından seçildiğinde
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yükselir. `VCC3V3_AUX` ise U12 üzerinden SYS5 var olduğu sürece
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supervisor/debug mantığını besler.
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J1'in kendi TUSB320'si (U5) yalnızca CC Rd terminasyonu ve UFP algılaması
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için kalır; onun OUT1/OUT2 çıkışları artık hiçbir mantığı sürmez, çünkü J1
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gücü hiçbir zaman SYS5'e taşımaz. J1'in VBUS pini yalnızca iki yerel bölücüyü
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besler: U5'in `VBUS_DET` girişi ve FT4232H'nin self-powered
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`FTDI_RESET_N` algılaması. Böylece FT4232H, J1'e gerçek bir USB host
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takılmadığı sürece resette kalır; bu davranış J7 veya J3 üzerinden kart
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güçlendirilmiş olsa bile değişmez.
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## Ray üretimi
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| Sıra | Ray | Regülatör | Nominal kapasite | Yükler |
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+26
-7
@@ -15,8 +15,10 @@ ara çalışma ürünleridir; kalıcı kararların kaynağı ilgili scriptler ve
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## Güç mimarisi
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1. USB-C VBUS veya harici 5 V koruma ve power-path devresinden sonra `SYS5`
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rayını oluşturur.
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1. Dedike USB-C güç girişi J7'nin VBUS'ı veya harici 5 V girişi J3, koruma ve
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power-path devresinden sonra `SYS5` rayını oluşturur; ikisi aynı anda
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bağlıysa TPS2121 yalnızca birini seçer, asla toplanmaz. JTAG/UART debug
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portu J1 bu yola hiç dahil değildir ve SYS5'i beslemez.
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2. TPS6287B15, FPGA core/VCCA/VDD_SOC için 0.95 V üretir.
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3. `CORE_PG`, LM3880 sıralayıcıyı başlatır.
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4. LM3880 önce TPS62867 1.8 V rayını, ardından TPS62867 3.3 V rayını etkinleştirir.
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@@ -91,11 +93,19 @@ yoktur.
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olarak kurulur; bu netler autorouter'a hiç verilmez. Yerlerini routing
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boyunca `TEMP_RF_LINE` ve `TEMP_USB_*` koridor rule area'ları tutar; bunlar
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F.Cu dahil bütün bakır katmanlarını kapsar ve finalde silinir.
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- GPS ön ucunun altında kalıcı bir `RF_NO_DIGITAL` rule area'sı vardır (L3, L5,
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L6, B.Cu). Kendisi bakır yasaklamaz; `board.kicad_dru` içindeki kural POWER
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dışı net sınıflarına track ve via yasağı koyar. Böylece ground stitching ve
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MAX2771'in kendi besleme inişleri geçebilirken, RF hattının altına veya hemen
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yanına sonradan elle bir digital hat çekilmesi DRC hatası olur.
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- RF hattının koridorunun altında kalıcı bir `RF_NO_DIGITAL` rule area'sı
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vardır (L3, L5, L6, B.Cu). Kendisi bakır yasaklamaz; `board.kicad_dru`
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içindeki kural POWER dışı net sınıflarına track ve via yasağı koyar. Böylece
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ground stitching ve MAX2771'in kendi besleme inişleri geçebilirken, RF
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hattının altına veya hemen yanına sonradan elle bir digital hat çekilmesi DRC
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hatası olur.
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- Alan (152, 36)-(174.5, 43.7) koridorudur; `generate_pcb.py`'nin `TEMP_RF_LINE`
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olarak ayırdığı koridorun aynısı. RF bakırı y <= 42.6'da kaldığı için 1.1 mm
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açık kalır. Alan bilerek MAX2771'in dijital pin sıralarında (y = 44.5 .. 47.4)
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durur: o pinlerin FPGA'ya ulaşması gerekir ve alan onların üstüne
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uzatıldığında hepsi yalnız F.Cu'ya sıkışıyor, sığmıyordu. RF dönüş yolu zaten
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bu alan tarafından değil, üzerinde hiç route edilmeyen L2/L7 GND plane'leri
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tarafından garanti edilir.
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- L2 ve L7 kesintisiz GND referans katmanlarıdır ve hiçbir şey route edilmez;
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dört routing katmanının her birinin komşusunda bir tanesi bulunur.
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- Hiçbir ray tek başına bir katman harcamaz. DC güç L4 ve L6'ya bölünmüş zone
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@@ -108,6 +118,15 @@ yoktur.
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- Plane'i olmayan küçük raylar ve plane adasının dışında kalan güç pad'leri
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`scripts/route_local_power.py` tarafından kilitli, 45 derecelik kısa yollarla
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tamamlanır. Bu iş autorouter'a bırakılmaz.
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- Ti375 escape alanı içinde bakır, kartın geri kalanının zaten kullandığı
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0.10 mm clearance'ta çalışır (`Ti375 escape field copper clearance` kuralı,
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her iki nesne de U1 courtyard'ının içindeyken). 0.8 mm pitch, iki komşu
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||||
0.45 mm dogbone via arasında 0.35 mm bırakır; CLOCK sınıfının 0.15 mm'si
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orada bir clock balını paketten hiç çıkaramaz. Clock trunk, courtyard'ın
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dışına çıkar çıkmaz 0.15 mm genişlik ve clearance'ına döner.
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- Escape alanının içinde kalan kısa güç inişleri 0.10 mm'dir; en kötü hâlde
|
||||
(VCC3V0_DIG bank besleme balı) uçtan uca yaklaşık 150 mOhm eder, 100 mA'de
|
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15 mV. Bu balların yanında yerel decoupling vardır.
|
||||
|
||||
## Güç dağıtımı kuralı
|
||||
|
||||
|
||||
@@ -5100,4 +5100,85 @@ X A 2 700 0 200 L 30 30 1 1 P
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||||
ENDDRAW
|
||||
ENDDEF
|
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#
|
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# BOARD_J7
|
||||
#
|
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DEF BOARD_J7 J 0 30 Y Y 1 L N
|
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F0 "J7" 0 200 50 H V C CNN
|
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F1 "USB-C power input" 0 100 50 H V C CNN
|
||||
F2 "Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal" 0 -100 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -500 500 500 -500 1 1 10 f
|
||||
X GND A1 -700 400 200 R 30 30 1 1 P
|
||||
X VBUS A4 700 350 200 L 30 30 1 1 P
|
||||
X CC1 A5 -700 300 200 R 30 30 1 1 P
|
||||
X D A6 700 250 200 L 30 30 1 1 P
|
||||
X D A7 -700 200 200 R 30 30 1 1 P
|
||||
X SBU1 A8 700 150 200 L 30 30 1 1 P
|
||||
X VBUS A9 -700 100 200 R 30 30 1 1 P
|
||||
X GND A12 700 50 200 L 30 30 1 1 P
|
||||
X GND B1 -700 0 200 R 30 30 1 1 P
|
||||
X VBUS B4 700 -50 200 L 30 30 1 1 P
|
||||
X CC2 B5 -700 -100 200 R 30 30 1 1 P
|
||||
X D B6 700 -150 200 L 30 30 1 1 P
|
||||
X D B7 -700 -200 200 R 30 30 1 1 P
|
||||
X SBU2 B8 700 -250 200 L 30 30 1 1 P
|
||||
X VBUS B9 -700 -300 200 R 30 30 1 1 P
|
||||
X GND B12 700 -350 200 L 30 30 1 1 P
|
||||
X SHIELD SH -700 -400 200 R 30 30 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# BOARD_U35
|
||||
#
|
||||
DEF BOARD_U35 U 0 30 Y Y 1 L N
|
||||
F0 "U35" 0 200 50 H V C CNN
|
||||
F1 "TUSB320LAI" 0 100 50 H V C CNN
|
||||
F2 "Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm" 0 -100 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -500 350 500 -350 1 1 10 f
|
||||
X CC1 1 -700 250 200 R 30 30 1 1 B
|
||||
X CC2 2 700 250 200 L 30 30 1 1 B
|
||||
X PORT 3 -700 150 200 R 30 30 1 1 I
|
||||
X VBUS_DET 4 700 150 200 L 30 30 1 1 I
|
||||
X ADDR 5 -700 50 200 R 30 30 1 1 P
|
||||
X OUT3 6 700 50 200 L 30 30 1 1 O
|
||||
X OUT1 7 -700 -50 200 R 30 30 1 1 O
|
||||
X OUT2 8 700 -50 200 L 30 30 1 1 O
|
||||
X ID 9 -700 -150 200 R 30 30 1 1 O
|
||||
X GND 10 700 -150 200 L 30 30 1 1 W
|
||||
X EN_N 11 -700 -250 200 R 30 30 1 1 I
|
||||
X VDD 12 700 -250 200 L 30 30 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# BOARD_R107
|
||||
#
|
||||
DEF BOARD_R107 R 0 30 Y Y 1 L N
|
||||
F0 "R107" 0 200 50 H V C CNN
|
||||
F1 "900K" 0 100 50 H V C CNN
|
||||
F2 "Resistor_SMD:R_0402_1005Metric" 0 -100 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -500 150 500 -150 1 1 10 f
|
||||
X 1 1 -700 0 200 R 30 30 1 1 P
|
||||
X 2 2 700 0 200 L 30 30 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# BOARD_C129
|
||||
#
|
||||
DEF BOARD_C129 C 0 30 Y Y 1 L N
|
||||
F0 "C129" 0 200 50 H V C CNN
|
||||
F1 "100nF" 0 100 50 H V C CNN
|
||||
F2 "Capacitor_SMD:C_0402_1005Metric" 0 -100 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -500 150 500 -150 1 1 10 f
|
||||
X 1 1 -700 0 200 R 30 30 1 1 P
|
||||
X 2 2 700 0 200 L 30 30 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
|
||||
@@ -29,7 +29,7 @@
|
||||
(condition "A.Reference == 'U1' || B.Reference == 'U1'")
|
||||
(constraint clearance (min 0.10mm)))
|
||||
|
||||
# JLC08161H-3313 L1/L2 geometry. Net-class widths are routing defaults only;
|
||||
# JLC10161H L1/L2 geometry (F->L2 prepreg unchanged from the 8L build). Net-class widths are routing defaults only;
|
||||
# these rules make the controlled-impedance geometries actual DRC limits.
|
||||
(rule "GNSS 50-ohm CPWG geometry"
|
||||
(condition "A.NetClass == 'RF50_CPWG'")
|
||||
@@ -50,12 +50,19 @@
|
||||
(condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair() && !A.intersectsArea('USB_ESD_BREAKOUT')")
|
||||
(constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.90mm)))
|
||||
|
||||
# The GPS front end owns its region on every layer under F.Cu, so no digital
|
||||
# route can run beneath or immediately beside the 50-ohm line and no return
|
||||
# path there is broken. Ground stitching and the MAX2771's own supply drops
|
||||
# still have to reach it, so the disallow is scoped to the signal classes
|
||||
# rather than made a plain keepout. The RF line itself is on F.Cu, which the
|
||||
# area does not cover, and L2/L7 stay solid because nothing routes on them.
|
||||
# The 50-ohm line owns the band it runs in on every layer under F.Cu, so no
|
||||
# digital route can pass beneath or immediately beside it. Ground stitching
|
||||
# and the MAX2771's own supply drops still have to reach it, so the disallow is
|
||||
# scoped to the signal classes rather than made a plain keepout. The RF line
|
||||
# itself is on F.Cu, which the area does not cover, and the L2/L7 GND planes
|
||||
# stay solid because nothing routes on them at all -- the actual RF return path
|
||||
# is guaranteed by those planes, not by this area.
|
||||
#
|
||||
# The area covers y <= 43.7, which is the same corridor generate_pcb.py
|
||||
# reserves as TEMP_RF_LINE and clears the RF copper (y <= 42.6) by 1.1 mm. It
|
||||
# deliberately stops short of the MAX2771's digital pin rows at y = 44.5 ..
|
||||
# 47.4: those pins have to reach the FPGA, and with the area extended over them
|
||||
# every one of them was forced onto F.Cu alone, which does not fit.
|
||||
(rule "No digital copper under the GNSS front end"
|
||||
(condition "A.intersectsArea('RF_NO_DIGITAL') && A.NetClass != 'POWER'")
|
||||
(constraint disallow track via))
|
||||
@@ -63,3 +70,15 @@
|
||||
(rule "Clock trunk width outside Ti375 escape"
|
||||
(condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')")
|
||||
(constraint track_width (min 0.15mm)))
|
||||
|
||||
# A 0.8-mm ball pitch leaves a 0.35-mm channel between two adjacent 0.45-mm
|
||||
# dogbone vias. A 0.10-mm trace fits that channel at the escape field's
|
||||
# 0.10-mm copper minimum but not at CLOCK's 0.15 mm, so a clock ball could not
|
||||
# be escaped from the package at all. Inside the field -- and only where BOTH
|
||||
# objects are inside it -- copper therefore runs at the same 0.10 mm the rest
|
||||
# of this field already uses. The clock trunk keeps its 0.15 mm the moment it
|
||||
# leaves U1's courtyard, which is where coupling to neighbours actually costs
|
||||
# something.
|
||||
(rule "Ti375 escape field copper clearance"
|
||||
(condition "A.insideCourtyard('U1') && B.insideCourtyard('U1')")
|
||||
(constraint clearance (min 0.10mm)))
|
||||
|
||||
+63003
-60143
File diff suppressed because it is too large
Load Diff
@@ -563,7 +563,13 @@
|
||||
"bus_aliases": {},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"top_level_sheets": []
|
||||
"top_level_sheets": [
|
||||
{
|
||||
"filename": "board.kicad_sch",
|
||||
"name": "board",
|
||||
"uuid": "00000000-0000-0000-0000-000000000000"
|
||||
}
|
||||
]
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {},
|
||||
|
||||
+4597
-4109
File diff suppressed because it is too large
Load Diff
+250
-2
@@ -2426,7 +2426,7 @@
|
||||
(property "Manufacturer" "GCT" (id 5) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Description" "USB 2.0 Type-C receptacle, UFP/sink" (id 6) (at 0.0 0.0 0)
|
||||
(property "Description" "USB 2.0 Type-C receptacle, UFP/sink, debug data only" (id 6) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(symbol "BOARD_J1_1_1"
|
||||
@@ -2523,7 +2523,7 @@
|
||||
(property "Manufacturer" "Texas Instruments" (id 5) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Description" "USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2" (id 6) (at 0.0 0.0 0)
|
||||
(property "Description" "USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2; current-advertisement outputs unused since this port never sources SYS5" (id 6) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(symbol "BOARD_U5_1_1"
|
||||
@@ -14664,6 +14664,254 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "BOARD_J7" (pin_names (offset 0.508)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "J" (id 0) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "USB-C power input" (id 1) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal" (id 2) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (id 3) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "MPN" "USB4105-GF-A-120" (id 4) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Manufacturer" "GCT" (id 5) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Description" "USB 2.0 Type-C receptacle, UFP/sink, power input only" (id 6) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(symbol "BOARD_J7_1_1"
|
||||
(rectangle (start -12.7 -12.7) (end 12.7 12.7)
|
||||
(stroke (width 0.254) (type default))
|
||||
(fill (type background))
|
||||
)
|
||||
(pin passive line (at -17.78 -10.16 0) (length 5.08)
|
||||
(name "GND" (effects (font (size 0.65 0.65))))
|
||||
(number "A1" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 -8.89 180) (length 5.08)
|
||||
(name "VBUS" (effects (font (size 0.65 0.65))))
|
||||
(number "A4" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 -7.62 0) (length 5.08)
|
||||
(name "CC1" (effects (font (size 0.65 0.65))))
|
||||
(number "A5" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 -6.3500000000000005 180) (length 5.08)
|
||||
(name "D+" (effects (font (size 0.65 0.65))))
|
||||
(number "A6" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 -5.08 0) (length 5.08)
|
||||
(name "D-" (effects (font (size 0.65 0.65))))
|
||||
(number "A7" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 -3.8100000000000005 180) (length 5.08)
|
||||
(name "SBU1" (effects (font (size 0.65 0.65))))
|
||||
(number "A8" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 -2.54 0) (length 5.08)
|
||||
(name "VBUS" (effects (font (size 0.65 0.65))))
|
||||
(number "A9" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 -1.2700000000000005 180) (length 5.08)
|
||||
(name "GND" (effects (font (size 0.65 0.65))))
|
||||
(number "A12" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 0.0 0) (length 5.08)
|
||||
(name "GND" (effects (font (size 0.65 0.65))))
|
||||
(number "B1" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 1.2699999999999996 180) (length 5.08)
|
||||
(name "VBUS" (effects (font (size 0.65 0.65))))
|
||||
(number "B4" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 2.539999999999999 0) (length 5.08)
|
||||
(name "CC2" (effects (font (size 0.65 0.65))))
|
||||
(number "B5" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 3.8099999999999987 180) (length 5.08)
|
||||
(name "D+" (effects (font (size 0.65 0.65))))
|
||||
(number "B6" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 5.08 0) (length 5.08)
|
||||
(name "D-" (effects (font (size 0.65 0.65))))
|
||||
(number "B7" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 6.35 180) (length 5.08)
|
||||
(name "SBU2" (effects (font (size 0.65 0.65))))
|
||||
(number "B8" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 7.620000000000001 0) (length 5.08)
|
||||
(name "VBUS" (effects (font (size 0.65 0.65))))
|
||||
(number "B9" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 8.89 180) (length 5.08)
|
||||
(name "GND" (effects (font (size 0.65 0.65))))
|
||||
(number "B12" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 10.16 0) (length 5.08)
|
||||
(name "SHIELD" (effects (font (size 0.65 0.65))))
|
||||
(number "SH" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "BOARD_U35" (pin_names (offset 0.508)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "U" (id 0) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "TUSB320LAI" (id 1) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm" (id 2) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (id 3) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "MPN" "TUSB320LAIRSW(R)" (id 4) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Manufacturer" "Texas Instruments" (id 5) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Description" "USB Type-C port controller in UFP GPIO mode for the power input; integrated Rd on CC1/CC2; OUT1/OUT2 3-A advertisement drives U10/U11 MAIN_EN gating" (id 6) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(symbol "BOARD_U35_1_1"
|
||||
(rectangle (start -12.7 -8.89) (end 12.7 8.89)
|
||||
(stroke (width 0.254) (type default))
|
||||
(fill (type background))
|
||||
)
|
||||
(pin bidirectional line (at -17.78 -6.35 0) (length 5.08)
|
||||
(name "CC1" (effects (font (size 0.65 0.65))))
|
||||
(number "1" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin bidirectional line (at 17.78 -6.35 180) (length 5.08)
|
||||
(name "CC2" (effects (font (size 0.65 0.65))))
|
||||
(number "2" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin input line (at -17.78 -3.8099999999999996 0) (length 5.08)
|
||||
(name "PORT" (effects (font (size 0.65 0.65))))
|
||||
(number "3" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin input line (at 17.78 -3.8099999999999996 180) (length 5.08)
|
||||
(name "VBUS_DET" (effects (font (size 0.65 0.65))))
|
||||
(number "4" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at -17.78 -1.2699999999999996 0) (length 5.08)
|
||||
(name "ADDR" (effects (font (size 0.65 0.65))))
|
||||
(number "5" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin output line (at 17.78 -1.2699999999999996 180) (length 5.08)
|
||||
(name "OUT3" (effects (font (size 0.65 0.65))))
|
||||
(number "6" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin output line (at -17.78 1.2700000000000005 0) (length 5.08)
|
||||
(name "OUT1" (effects (font (size 0.65 0.65))))
|
||||
(number "7" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin output line (at 17.78 1.2700000000000005 180) (length 5.08)
|
||||
(name "OUT2" (effects (font (size 0.65 0.65))))
|
||||
(number "8" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin output line (at -17.78 3.8100000000000005 0) (length 5.08)
|
||||
(name "ID" (effects (font (size 0.65 0.65))))
|
||||
(number "9" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin power_in line (at 17.78 3.8100000000000005 180) (length 5.08)
|
||||
(name "GND" (effects (font (size 0.65 0.65))))
|
||||
(number "10" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin input line (at -17.78 6.35 0) (length 5.08)
|
||||
(name "EN_N" (effects (font (size 0.65 0.65))))
|
||||
(number "11" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin power_in line (at 17.78 6.35 180) (length 5.08)
|
||||
(name "VDD" (effects (font (size 0.65 0.65))))
|
||||
(number "12" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "BOARD_R107" (pin_names (offset 0.508)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "R" (id 0) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "900K" (id 1) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (id 3) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "MPN" "RC0402FR-07909KL" (id 4) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Manufacturer" "Yageo" (id 5) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Description" "TUSB320 VBUS_DET current limiter" (id 6) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(symbol "BOARD_R107_1_1"
|
||||
(rectangle (start -12.7 -3.81) (end 12.7 3.81)
|
||||
(stroke (width 0.254) (type default))
|
||||
(fill (type background))
|
||||
)
|
||||
(pin passive line (at -17.78 0.0 0) (length 5.08)
|
||||
(name "1" (effects (font (size 0.65 0.65))))
|
||||
(number "1" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 0.0 180) (length 5.08)
|
||||
(name "2" (effects (font (size 0.65 0.65))))
|
||||
(number "2" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "BOARD_C129" (pin_names (offset 0.508)) (in_bom yes) (on_board yes)
|
||||
(property "Reference" "C" (id 0) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Value" "100nF" (id 1) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
)
|
||||
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "Datasheet" "" (id 3) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)) hide)
|
||||
)
|
||||
(property "MPN" "GRM155R71A104KA01D" (id 4) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Manufacturer" "Murata" (id 5) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(property "Description" "TUSB320 local bypass" (id 6) (at 0.0 0.0 0)
|
||||
(effects (font (size 0.8 0.8)) hide)
|
||||
)
|
||||
(symbol "BOARD_C129_1_1"
|
||||
(rectangle (start -12.7 -3.81) (end 12.7 3.81)
|
||||
(stroke (width 0.254) (type default))
|
||||
(fill (type background))
|
||||
)
|
||||
(pin passive line (at -17.78 0.0 0) (length 5.08)
|
||||
(name "1" (effects (font (size 0.65 0.65))))
|
||||
(number "1" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
(pin passive line (at 17.78 0.0 180) (length 5.08)
|
||||
(name "2" (effects (font (size 0.65 0.65))))
|
||||
(number "2" (effects (font (size 0.65 0.65))))
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol "PWR_FLAG" (power) (in_bom no) (on_board no)
|
||||
(property "Reference" "#FLG" (id 0) (at 0.0 0.0 0)
|
||||
(effects (font (size 1.27 1.27)))
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
(version 1)
|
||||
|
||||
# The edge-launch SMA copper must reach the routed board edge by construction.
|
||||
(rule "J2 edge-launch lands"
|
||||
(condition "A.Reference == 'J2' || B.Reference == 'J2'")
|
||||
(constraint edge_clearance (min -0.01mm)))
|
||||
|
||||
# The manufacturer USB-C locating holes are 0.194 mm from grounded shell
|
||||
# lands. This exception is internal to the qualified connector footprint.
|
||||
(rule "USB-C locating-hole clearance"
|
||||
(condition "A.Reference == 'J1' && B.Reference == 'J1'")
|
||||
(constraint hole_clearance (min 0.19mm)))
|
||||
|
||||
# RZV0024A is an ultra-dense high-current package. Its adjusted corner lands
|
||||
# and thermal zones meet the selected JLCPCB 0.10-mm copper rule.
|
||||
(rule "TPS6287B RZV internal clearance"
|
||||
(condition "A.Reference == 'U13' && B.Reference == 'U13'")
|
||||
(constraint clearance (min 0.10mm)))
|
||||
|
||||
# Inside the Ti375 escape field the 0.8-mm ball pitch fixes the geometry: a
|
||||
# 0.45-mm dogbone via between four lands leaves 0.1407 mm, and a 0.12-mm trace
|
||||
# threading between two lands leaves 0.14 mm only if it stays exactly centred.
|
||||
# This field therefore runs at the fabricator's 0.10-mm copper minimum, which
|
||||
# is what the Default class uses across the rest of the board anyway. The rule
|
||||
# only fires when one of the two objects belongs to U1, so it relaxes copper
|
||||
# against the balls and nothing else: two tracks crossing the field still owe
|
||||
# each other their own net classes' clearance, CLOCK's 0.15 mm included.
|
||||
(rule "Ti375 0.8-mm BGA escape clearance"
|
||||
(condition "A.Reference == 'U1' || B.Reference == 'U1'")
|
||||
(constraint clearance (min 0.10mm)))
|
||||
|
||||
# JLC10161H L1/L2 geometry (F->L2 prepreg unchanged from the 8L build). Net-class widths are routing defaults only;
|
||||
# these rules make the controlled-impedance geometries actual DRC limits.
|
||||
(rule "GNSS 50-ohm CPWG geometry"
|
||||
(condition "A.NetClass == 'RF50_CPWG'")
|
||||
(constraint track_width (min 0.164mm) (opt 0.164mm) (max 0.164mm)))
|
||||
|
||||
(rule "GNSS RF stays on top layer"
|
||||
(condition "A.NetClass == 'RF50_CPWG' && A.Type == 'Track' && A.Layer != 'F.Cu'")
|
||||
(constraint disallow track))
|
||||
|
||||
(rule "USB2 90-ohm differential geometry"
|
||||
(condition "A.NetClass == 'USB90_DIFF'")
|
||||
(constraint track_width (min 0.135mm) (opt 0.135mm) (max 0.135mm)))
|
||||
|
||||
# The TPD2EUSB30A clamp is a SOT-23 whose ground pad sits between its two
|
||||
# channel pads, so the pair has to open up for about 1.5 mm to pass it. The
|
||||
# 0.90-mm coupled limit still applies over the whole rest of the run.
|
||||
(rule "USB2 coupled gap"
|
||||
(condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair() && !A.intersectsArea('USB_ESD_BREAKOUT')")
|
||||
(constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.90mm)))
|
||||
|
||||
# The 50-ohm line owns the band it runs in on every layer under F.Cu, so no
|
||||
# digital route can pass beneath or immediately beside it. Ground stitching
|
||||
# and the MAX2771's own supply drops still have to reach it, so the disallow is
|
||||
# scoped to the signal classes rather than made a plain keepout. The RF line
|
||||
# itself is on F.Cu, which the area does not cover, and the L2/L7 GND planes
|
||||
# stay solid because nothing routes on them at all -- the actual RF return path
|
||||
# is guaranteed by those planes, not by this area.
|
||||
#
|
||||
# The area covers y <= 43.7, which is the same corridor generate_pcb.py
|
||||
# reserves as TEMP_RF_LINE and clears the RF copper (y <= 42.6) by 1.1 mm. It
|
||||
# deliberately stops short of the MAX2771's digital pin rows at y = 44.5 ..
|
||||
# 47.4: those pins have to reach the FPGA, and with the area extended over them
|
||||
# every one of them was forced onto F.Cu alone, which does not fit.
|
||||
(rule "No digital copper under the GNSS front end"
|
||||
(condition "A.intersectsArea('RF_NO_DIGITAL') && A.NetClass != 'POWER'")
|
||||
(constraint disallow track via))
|
||||
|
||||
(rule "Clock trunk width outside Ti375 escape"
|
||||
(condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')")
|
||||
(constraint track_width (min 0.15mm)))
|
||||
|
||||
# A 0.8-mm ball pitch leaves a 0.35-mm channel between two adjacent 0.45-mm
|
||||
# dogbone vias. A 0.10-mm trace fits that channel at the escape field's
|
||||
# 0.10-mm copper minimum but not at CLOCK's 0.15 mm, so a clock ball could not
|
||||
# be escaped from the package at all. Inside the field -- and only where BOTH
|
||||
# objects are inside it -- copper therefore runs at the same 0.10 mm the rest
|
||||
# of this field already uses. The clock trunk keeps its 0.15 mm the moment it
|
||||
# leaves U1's courtyard, which is where coupling to neighbours actually costs
|
||||
# something.
|
||||
(rule "Ti375 escape field copper clearance"
|
||||
(condition "A.insideCourtyard('U1') && B.insideCourtyard('U1')")
|
||||
(constraint clearance (min 0.10mm)))
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,582 @@
|
||||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"apply_defaults_to_fp_barcodes": false,
|
||||
"apply_defaults_to_fp_dimensions": false,
|
||||
"apply_defaults_to_fp_fields": false,
|
||||
"apply_defaults_to_fp_shapes": false,
|
||||
"apply_defaults_to_fp_text": false,
|
||||
"board_outline_line_width": 0.05,
|
||||
"copper_line_width": 0.2,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.05,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": true,
|
||||
"text_position": 0,
|
||||
"units_format": 0
|
||||
},
|
||||
"fab_line_width": 0.1,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.1,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.8,
|
||||
"height": 1.27,
|
||||
"width": 1.27
|
||||
},
|
||||
"silk_line_width": 0.1,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.1,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"border_display_style": 2,
|
||||
"border_hatch_pitch": 0.5,
|
||||
"corner_radius": 0.0,
|
||||
"corner_smoothing": 0,
|
||||
"fill_mode": 0,
|
||||
"hatch_gap": 1.5,
|
||||
"hatch_orientation": 0.0,
|
||||
"hatch_smoothing_level": 0,
|
||||
"hatch_smoothing_value": 0.1,
|
||||
"hatch_thickness": 1.0,
|
||||
"min_clearance": 0.5,
|
||||
"min_island_area": 10.0,
|
||||
"min_thickness": 0.25,
|
||||
"pad_connection": 1,
|
||||
"remove_islands": 0,
|
||||
"thermal_relief_gap": 0.5,
|
||||
"thermal_relief_spoke_width": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"creepage": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_filters_mismatch": "ignore",
|
||||
"footprint_symbol_field_mismatch": "warning",
|
||||
"footprint_symbol_mismatch": "warning",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_to_hole": "warning",
|
||||
"holes_co_located": "warning",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"mirrored_text_on_front_layer": "warning",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"missing_tuning_profile": "warning",
|
||||
"net_conflict": "warning",
|
||||
"nonmirrored_text_on_back_layer": "warning",
|
||||
"npth_inside_courtyard": "error",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "error",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_on_edge_cuts": "error",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_angle": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_not_centered_on_via": "ignore",
|
||||
"track_on_post_machined_layer": "error",
|
||||
"track_segment_length": "error",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"tuning_profile_track_geometries": "ignore",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.1,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.25,
|
||||
"min_groove_width": 0.0,
|
||||
"min_hole_clearance": 0.19,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.2,
|
||||
"min_microvia_drill": 0.1,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.8,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.225,
|
||||
"min_track_width": 0.1,
|
||||
"min_via_annular_width": 0.1,
|
||||
"min_via_diameter": 0.45,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_onpthpad": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_onsmdpad": true,
|
||||
"td_ontrackend": false,
|
||||
"td_onvia": true
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [],
|
||||
"tuning_pattern_settings": {
|
||||
"diff_pair_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 1.0
|
||||
},
|
||||
"diff_pair_skew_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
},
|
||||
"single_track_defaults": {
|
||||
"corner_radius_percentage": 80,
|
||||
"corner_style": 1,
|
||||
"max_amplitude": 1.0,
|
||||
"min_amplitude": 0.2,
|
||||
"single_sided": false,
|
||||
"spacing": 0.6
|
||||
}
|
||||
},
|
||||
"via_dimensions": [],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"ipc2581": {
|
||||
"bom_rev": "",
|
||||
"dist": "",
|
||||
"distpn": "",
|
||||
"internal_id": "",
|
||||
"mfg": "",
|
||||
"mpn": "",
|
||||
"sch_revision": ""
|
||||
},
|
||||
"layer_pairs": [],
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"component_class_settings": {
|
||||
"assignments": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"sheet_component_classes": {
|
||||
"enabled": false
|
||||
}
|
||||
},
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "board_routed.kicad_pro",
|
||||
"version": 3
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.1,
|
||||
"diff_pair_gap": 0.15,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.135,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2147483647,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.12,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.45,
|
||||
"via_drill": 0.225,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.1,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "BGA_ESCAPE",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": -1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.1,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.45,
|
||||
"via_drill": 0.225,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.15,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "CLOCK",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": -1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.15,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.45,
|
||||
"via_drill": 0.225,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.1,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "POWER",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": -1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.4,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.45,
|
||||
"via_drill": 0.225,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "RF50_CPWG",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": -1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.164,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.45,
|
||||
"via_drill": 0.225,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.15,
|
||||
"diff_pair_gap": 0.15,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.135,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "USB90_DIFF",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": -1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.135,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.45,
|
||||
"via_drill": 0.225,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 5
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": [
|
||||
{
|
||||
"netclass": "RF50_CPWG",
|
||||
"pattern": "RF_SMA"
|
||||
},
|
||||
{
|
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161,
|
||||
38.7
|
||||
],
|
||||
[
|
||||
163,
|
||||
38.7
|
||||
],
|
||||
[
|
||||
165,
|
||||
38.7
|
||||
],
|
||||
[
|
||||
167,
|
||||
38.7
|
||||
],
|
||||
[
|
||||
169,
|
||||
38.7
|
||||
],
|
||||
[
|
||||
171,
|
||||
38.7
|
||||
],
|
||||
[
|
||||
173,
|
||||
38.7
|
||||
],
|
||||
[
|
||||
161,
|
||||
45.0
|
||||
],
|
||||
[
|
||||
163,
|
||||
45.0
|
||||
],
|
||||
[
|
||||
165,
|
||||
45.0
|
||||
],
|
||||
[
|
||||
167,
|
||||
45.0
|
||||
],
|
||||
[
|
||||
169,
|
||||
45.0
|
||||
],
|
||||
[
|
||||
171,
|
||||
45.0
|
||||
],
|
||||
[
|
||||
173,
|
||||
45.0
|
||||
]
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
+164
-13
@@ -34,7 +34,7 @@ GND
|
||||
Wire Wire Line
|
||||
2500 2150 2650 2150
|
||||
Text GLabel 2650 2150 0 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
DBG_VBUS_RAW
|
||||
Wire Wire Line
|
||||
1100 2100 950 2100
|
||||
Text GLabel 950 2100 2 30 BiDi ~ 0
|
||||
@@ -51,7 +51,7 @@ NoConn ~ 2500 1950
|
||||
Wire Wire Line
|
||||
1100 1900 950 1900
|
||||
Text GLabel 950 1900 2 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
DBG_VBUS_RAW
|
||||
Wire Wire Line
|
||||
2500 1850 2650 1850
|
||||
Text GLabel 2650 1850 0 30 BiDi ~ 0
|
||||
@@ -63,7 +63,7 @@ GND
|
||||
Wire Wire Line
|
||||
2500 1750 2650 1750
|
||||
Text GLabel 2650 1750 0 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
DBG_VBUS_RAW
|
||||
Wire Wire Line
|
||||
1100 1700 950 1700
|
||||
Text GLabel 950 1700 2 30 BiDi ~ 0
|
||||
@@ -80,7 +80,7 @@ NoConn ~ 2500 1550
|
||||
Wire Wire Line
|
||||
1100 1500 950 1500
|
||||
Text GLabel 950 1500 2 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
DBG_VBUS_RAW
|
||||
Wire Wire Line
|
||||
2500 1450 2650 1450
|
||||
Text GLabel 2650 1450 0 30 BiDi ~ 0
|
||||
@@ -120,14 +120,8 @@ Text GLabel 2650 3450 0 30 BiDi ~ 0
|
||||
USB_VBUS_DET
|
||||
NoConn ~ 1100 3350
|
||||
NoConn ~ 2500 3350
|
||||
Wire Wire Line
|
||||
1100 3250 950 3250
|
||||
Text GLabel 950 3250 2 30 BiDi ~ 0
|
||||
TUSB_OUT1
|
||||
Wire Wire Line
|
||||
2500 3250 2650 3250
|
||||
Text GLabel 2650 3250 0 30 BiDi ~ 0
|
||||
TUSB_OUT2
|
||||
NoConn ~ 1100 3250
|
||||
NoConn ~ 2500 3250
|
||||
NoConn ~ 1100 3150
|
||||
Wire Wire Line
|
||||
2500 3150 2650 3150
|
||||
@@ -157,7 +151,7 @@ $EndComp
|
||||
Wire Wire Line
|
||||
1100 4500 950 4500
|
||||
Text GLabel 950 4500 2 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
DBG_VBUS_RAW
|
||||
Wire Wire Line
|
||||
2500 4500 2650 4500
|
||||
Text GLabel 2650 4500 0 30 BiDi ~ 0
|
||||
@@ -4555,4 +4549,161 @@ Wire Wire Line
|
||||
17500 12200 17650 12200
|
||||
Text GLabel 17650 12200 0 30 BiDi ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L BOARD_J7 J7
|
||||
U 1 1 650100C4
|
||||
P 16800 13000
|
||||
F 0 "J7" H 16800 12900 50 0000 C CNN
|
||||
F 1 "USB-C power input" H 16800 13100 50 0000 C CNN
|
||||
F 2 "Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal" H 16800 12800 50 0001 C CNN
|
||||
F 3 "" H 16800 13000 50 0001 C CNN
|
||||
F 4 "USB4105-GF-A-120" H 16800 13000 50 0001 C CNN "MPN"
|
||||
F 5 "GCT" H 16800 13000 50 0001 C CNN "Manufacturer"
|
||||
1 16800 13000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
16100 13400 15950 13400
|
||||
Text GLabel 15950 13400 2 30 BiDi ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
17500 13350 17650 13350
|
||||
Text GLabel 17650 13350 0 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
Wire Wire Line
|
||||
16100 13300 15950 13300
|
||||
Text GLabel 15950 13300 2 30 BiDi ~ 0
|
||||
PWR_CC1
|
||||
NoConn ~ 17500 13250
|
||||
NoConn ~ 16100 13200
|
||||
NoConn ~ 17500 13150
|
||||
Wire Wire Line
|
||||
16100 13100 15950 13100
|
||||
Text GLabel 15950 13100 2 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
Wire Wire Line
|
||||
17500 13050 17650 13050
|
||||
Text GLabel 17650 13050 0 30 BiDi ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
16100 13000 15950 13000
|
||||
Text GLabel 15950 13000 2 30 BiDi ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
17500 12950 17650 12950
|
||||
Text GLabel 17650 12950 0 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
Wire Wire Line
|
||||
16100 12900 15950 12900
|
||||
Text GLabel 15950 12900 2 30 BiDi ~ 0
|
||||
PWR_CC2
|
||||
NoConn ~ 17500 12850
|
||||
NoConn ~ 16100 12800
|
||||
NoConn ~ 17500 12750
|
||||
Wire Wire Line
|
||||
16100 12700 15950 12700
|
||||
Text GLabel 15950 12700 2 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
Wire Wire Line
|
||||
17500 12650 17650 12650
|
||||
Text GLabel 17650 12650 0 30 BiDi ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
16100 12600 15950 12600
|
||||
Text GLabel 15950 12600 2 30 BiDi ~ 0
|
||||
USB_SHIELD
|
||||
$Comp
|
||||
L BOARD_U35 U35
|
||||
U 1 1 650100C5
|
||||
P 16800 14500
|
||||
F 0 "U35" H 16800 14400 50 0000 C CNN
|
||||
F 1 "TUSB320LAI" H 16800 14600 50 0000 C CNN
|
||||
F 2 "Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm" H 16800 14300 50 0001 C CNN
|
||||
F 3 "" H 16800 14500 50 0001 C CNN
|
||||
F 4 "TUSB320LAIRSW(R)" H 16800 14500 50 0001 C CNN "MPN"
|
||||
F 5 "Texas Instruments" H 16800 14500 50 0001 C CNN "Manufacturer"
|
||||
1 16800 14500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
16100 14750 15950 14750
|
||||
Text GLabel 15950 14750 2 30 BiDi ~ 0
|
||||
PWR_CC1
|
||||
Wire Wire Line
|
||||
17500 14750 17650 14750
|
||||
Text GLabel 17650 14750 0 30 BiDi ~ 0
|
||||
PWR_CC2
|
||||
Wire Wire Line
|
||||
16100 14650 15950 14650
|
||||
Text GLabel 15950 14650 2 30 BiDi ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
17500 14650 17650 14650
|
||||
Text GLabel 17650 14650 0 30 BiDi ~ 0
|
||||
PWR_USB_VBUS_DET
|
||||
NoConn ~ 16100 14550
|
||||
NoConn ~ 17500 14550
|
||||
Wire Wire Line
|
||||
16100 14450 15950 14450
|
||||
Text GLabel 15950 14450 2 30 BiDi ~ 0
|
||||
TUSB_OUT1
|
||||
Wire Wire Line
|
||||
17500 14450 17650 14450
|
||||
Text GLabel 17650 14450 0 30 BiDi ~ 0
|
||||
TUSB_OUT2
|
||||
NoConn ~ 16100 14350
|
||||
Wire Wire Line
|
||||
17500 14350 17650 14350
|
||||
Text GLabel 17650 14350 0 30 BiDi ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
16100 14250 15950 14250
|
||||
Text GLabel 15950 14250 2 30 BiDi ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
17500 14250 17650 14250
|
||||
Text GLabel 17650 14250 0 30 BiDi ~ 0
|
||||
VCC3V3_AUX
|
||||
$Comp
|
||||
L BOARD_R107 R107
|
||||
U 1 1 650100C6
|
||||
P 16800 15700
|
||||
F 0 "R107" H 16800 15600 50 0000 C CNN
|
||||
F 1 "900K" H 16800 15800 50 0000 C CNN
|
||||
F 2 "Resistor_SMD:R_0402_1005Metric" H 16800 15500 50 0001 C CNN
|
||||
F 3 "" H 16800 15700 50 0001 C CNN
|
||||
F 4 "RC0402FR-07909KL" H 16800 15700 50 0001 C CNN "MPN"
|
||||
F 5 "Yageo" H 16800 15700 50 0001 C CNN "Manufacturer"
|
||||
1 16800 15700
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
16100 15700 15950 15700
|
||||
Text GLabel 15950 15700 2 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
Wire Wire Line
|
||||
17500 15700 17650 15700
|
||||
Text GLabel 17650 15700 0 30 BiDi ~ 0
|
||||
PWR_USB_VBUS_DET
|
||||
$Comp
|
||||
L BOARD_C129 C129
|
||||
U 1 1 650100C7
|
||||
P 16800 16500
|
||||
F 0 "C129" H 16800 16400 50 0000 C CNN
|
||||
F 1 "100nF" H 16800 16600 50 0000 C CNN
|
||||
F 2 "Capacitor_SMD:C_0402_1005Metric" H 16800 16300 50 0001 C CNN
|
||||
F 3 "" H 16800 16500 50 0001 C CNN
|
||||
F 4 "GRM155R71A104KA01D" H 16800 16500 50 0001 C CNN "MPN"
|
||||
F 5 "Murata" H 16800 16500 50 0001 C CNN "Manufacturer"
|
||||
1 16800 16500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
16100 16500 15950 16500
|
||||
Text GLabel 15950 16500 2 30 BiDi ~ 0
|
||||
VCC3V3_AUX
|
||||
Wire Wire Line
|
||||
17500 16500 17650 16500
|
||||
Text GLabel 17650 16500 0 30 BiDi ~ 0
|
||||
GND
|
||||
$EndSCHEMATC
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
# Fixed-route data files
|
||||
|
||||
`power_routes.json` and `critical_routes.json` hold the **hand-drawn, audited
|
||||
geometry** that used to live in `scripts/route_power_stage.py` and the RF/USB
|
||||
block of `scripts/finalize_routing.py`. They are board-specific layout data —
|
||||
not an algorithm — consumed by the project-independent loader
|
||||
|
||||
```
|
||||
pcbrouter fixed --in <in.kicad_pcb> --out <out.kicad_pcb> --routes <file.json>
|
||||
```
|
||||
|
||||
which resolves the anchors against the board's footprints and splices locked
|
||||
copper, rule areas and the RF ground zone into the `.kicad_pcb`. Run
|
||||
`kicad-cli pcb drc --refill-zones` afterwards so the planes re-carve around the
|
||||
new vias (the Python scripts called `ZONE_FILLER.Fill()` for the same reason).
|
||||
|
||||
Regenerate from the (retired) scripts with
|
||||
`/usr/bin/python3 scripts/_extract_fixed_routes.py`.
|
||||
|
||||
## Schema
|
||||
|
||||
```jsonc
|
||||
{
|
||||
"tracks": [
|
||||
{
|
||||
"net": "CORE_SW", // net name (must exist on the board)
|
||||
"layer": "F.Cu", // KiCad canonical or user layer name
|
||||
"width": 0.20, // mm
|
||||
"points": [ "U13.9", [99.25, 95.25], [100.0, 95.25] ]
|
||||
// each point: "REF.PAD" anchor OR [x, y] mm
|
||||
}
|
||||
],
|
||||
"vias": [
|
||||
{ "net": "VCC0V95", "at": [107.8, 92.6], "diameter": 0.75, "drill": 0.38 }
|
||||
// "at" may also be a "REF.PAD" anchor
|
||||
],
|
||||
"rule_areas": [
|
||||
{ "name": "RF_NO_DIGITAL",
|
||||
"layers": ["B.Cu", "In2.Cu", "In4.Cu", "In5.Cu"],
|
||||
"rect": [152.0, 36.0, 174.5, 49.5] } // x0 y0 x1 y1 mm
|
||||
],
|
||||
"ground_zones": [
|
||||
{ "net": "GND", "layer": "F.Cu",
|
||||
"clearance": 0.20, "min_thickness": 0.10, "priority": 100,
|
||||
"outline": [[152.0,36.0],[174.5,36.0],[174.5,49.5],[152.0,49.5]],
|
||||
"via_fence": [[153,38.7],[155,38.7], ...] } // 0.45/0.225 GND vias
|
||||
]
|
||||
}
|
||||
```
|
||||
|
||||
All coordinates are millimetres in the board's own frame (KiCad screen-down Y).
|
||||
Anchors are resolved to the pad centre. Every emitted item is `(locked yes)`.
|
||||
@@ -271,7 +271,7 @@ $EndComp
|
||||
Wire Wire Line
|
||||
1100 7700 950 7700
|
||||
Text GLabel 950 7700 2 30 BiDi ~ 0
|
||||
VBUS_RAW
|
||||
DBG_VBUS_RAW
|
||||
Wire Wire Line
|
||||
2500 7700 2650 7700
|
||||
Text GLabel 2650 7700 0 30 BiDi ~ 0
|
||||
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 255 KiB After Width: | Height: | Size: 332 KiB |
+6
-4
@@ -1,5 +1,5 @@
|
||||
Reference,Qty,Value,Manufacturer,MPN,Footprint,Assembly,DNP,Description
|
||||
C1,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TUSB320 local bypass
|
||||
"C1,C129",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TUSB320 local bypass
|
||||
"C10,C11",2,47uF,Murata,GRM32ER70J476ME19L,Capacitor_SMD:C_1210_3225Metric,SMT,no,5-V system bulk
|
||||
C100,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,16.368-MHz TCXO bypass
|
||||
C101,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Clock-rail local bulk
|
||||
@@ -80,11 +80,12 @@ FB1,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,IM
|
||||
FB2,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,FTDI USB-PHY supply ferrite
|
||||
FB3,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,FTDI PLL supply ferrite
|
||||
FL1,1,GPS L1/L1C SAW,Kyocera,SF14-1582M5UUS2,board:Kyocera_SF14_5pad,SMT,no,"1565.19-1585.65-MHz SAW, 1.2-dB typical insertion loss"
|
||||
J1,1,USB-C USB2 sink,GCT,USB4105-GF-A-120,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,SMT,no,"USB 2.0 Type-C receptacle, UFP/sink"
|
||||
J1,1,USB-C USB2 sink,GCT,USB4105-GF-A-120,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,SMT,no,"USB 2.0 Type-C receptacle, UFP/sink, debug data only"
|
||||
J2,1,GPS L1 SMA,Amphenol RF,132289,Connector_Coaxial:SMA_Amphenol_132289_EdgeMount,THT,no,Edge-launch 50-ohm active GNSS antenna input
|
||||
J3,1,EXT_5V,Phoenix Contact,1935161,"TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal",THT,no,Clearly labelled external regulated 5-V input
|
||||
J4,1,EXT RESET_N,JST,SM02B-SRSS-TB(LF)(SN),Connector_JST:JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal,SMT,no,External active-low open-drain reset input; JST-SH 1.0-mm
|
||||
J5,1,ANT BIAS OFF/3V3/5V,Wuerth Elektronik,61300311121,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,THT,no,One-shunt hardware antenna bias selection; no shunt is OFF
|
||||
J7,1,USB-C power input,GCT,USB4105-GF-A-120,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,SMT,no,"USB 2.0 Type-C receptacle, UFP/sink, power input only"
|
||||
"JPMOD1,JPMOD2",2,PMOD 3.3 V,Amphenol ICC,67997-412HLF,board:Digilent_PMOD_2x6_P2.54mm,THT,no,"Digilent 2x6 PMOD: eight 3.3 V GPIO, two GND, two 3.3 V"
|
||||
"JPMOD3,JPMOD4",2,PMOD 1.8 V,Amphenol ICC,67997-412HLF,board:Digilent_PMOD_2x6_P2.54mm,THT,no,"Digilent 2x6 PMOD: eight 1.8 V GPIO, two GND, two 1.8 V"
|
||||
L1,1,100nH,Coilcraft,XEL4030-101MEC,board:Coilcraft_XEL4030,SMT,no,"Core inductor: 30-A saturation, 1.5-mohm DCR"
|
||||
@@ -134,7 +135,7 @@ R44,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,40-MHz ADC
|
||||
R55,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 remains shut down before FPGA configuration
|
||||
R56,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,40-MHz FPGA-clock source termination
|
||||
"R57,R58,R59",3,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,SafeSPI source-series damping
|
||||
R6,1,900K,Yageo,RC0402FR-07909KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 VBUS_DET current limiter
|
||||
"R6,R107",2,900K,Yageo,RC0402FR-07909KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 VBUS_DET current limiter
|
||||
R60,1,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,SafeSPI MISO source damping at IMU
|
||||
R61,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Hold IMU reset until FPGA releases it
|
||||
R62,1,27R,Yageo,RC0402FR-0727RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI USB D+ series termination
|
||||
@@ -204,7 +205,8 @@ U31,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,
|
||||
U32,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain all-rail-valid translation into FPGA CRESET_N
|
||||
U33,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain external/manual reset isolation into FPGA CRESET_N
|
||||
U34,1,SN74LVC08A,Texas Instruments,SN74LVC08APWR,Package_SO:TSSOP-14_4.4x5mm_P0.65mm,SMT,no,Always-on all-rail power-valid logic for reset release and debug isolation
|
||||
U5,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,SMT,no,USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2
|
||||
U35,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,SMT,no,USB Type-C port controller in UFP GPIO mode for the power input; integrated Rd on CC1/CC2; OUT1/OUT2 3-A advertisement drives U10/U11 MAIN_EN gating
|
||||
U5,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,SMT,no,USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2; current-advertisement outputs unused since this port never sources SYS5
|
||||
U6,1,TPD2EUSB30A,Texas Instruments,TPD2EUSB30ADRTR,Package_TO_SOT_SMD:Texas_DRT-3,SMT,no,Low-capacitance USB 2.0 ESD protection
|
||||
"U7,U8",2,TPS259470A,Texas Instruments,TPS259470ARPWR,board:Texas_RPW0010A_QFN10,SMT,no,True-reverse-blocking eFuse; UV/OV/current/inrush protection
|
||||
U9,1,TPS2121,Texas Instruments,TPS2121RUXR,board:Texas_RUX0012A_VQFN12,SMT,no,4.5-A power mux; external input wins near-equal valid 5-V inputs
|
||||
|
||||
|
+1994
-1994
File diff suppressed because it is too large
Load Diff
@@ -1,114 +1,10 @@
|
||||
** Drc report for board_routed.kicad_pcb **
|
||||
** Created on 2026-08-16T01:33:28 **
|
||||
** Report includes: Errors, Warnings **
|
||||
** Created on 2026-09-01T11:56:55 **
|
||||
** Report includes: Errors, Warnings, Exclusions **
|
||||
|
||||
** Found 0 DRC violations **
|
||||
|
||||
** Found 26 unconnected pads **
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(106.4000 mm, 65.6000 mm): Pad D10 [MAX_I0] of U1 on F.Cu
|
||||
@(154.6000 mm, 49.6900 mm): Pad 2 [MAX_I0] of R46 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(28.1950 mm, 51.2000 mm): Track [GND] on F.Cu, length 5.8400 mm
|
||||
@(30.8500 mm, 51.9250 mm): Pad 2 [GND] of U6 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(175.0000 mm, 46.2500 mm): Pad 2 [GND] of J2 on B.Cu
|
||||
@(175.0000 mm, 46.2500 mm): Pad 2 [GND] of J2 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(106.8000 mm, 64.4000 mm): Track [VCC3V0_DIG] on L3_SIG, length 1.4764 mm
|
||||
@(112.0000 mm, 68.8000 mm): Pad H17 [VCC3V0_DIG] of U1 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(112.0000 mm, 68.8000 mm): Pad H17 [VCC3V0_DIG] of U1 on F.Cu
|
||||
@(137.0000 mm, 70.0000 mm): Track [VCC3V0_DIG] on F.Cu, length 0.9050 mm
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(153.0459 mm, 42.6000 mm): Track [VCC3V0_RF] on F.Cu, length 2.3988 mm
|
||||
@(153.1000 mm, 44.0000 mm): Pad 2 [VCC3V0_RF] of U21 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(150.4900 mm, 44.5000 mm): Pad 1 [MAX_CLKOUT_SRC] of R45 on F.Cu
|
||||
@(153.1000 mm, 45.0000 mm): Pad 4 [MAX_CLKOUT_SRC] of U21 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(122.0100 mm, 65.5000 mm): Pad 2 [MAX_SCLK_DEV] of R51 on F.Cu
|
||||
@(154.0000 mm, 47.4000 mm): Pad 8 [MAX_SCLK_DEV] of U21 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(155.0000 mm, 47.4000 mm): Pad 10 [MAX_Q1_DEV] of U21 on F.Cu
|
||||
@(158.2000 mm, 50.7100 mm): Pad 1 [MAX_Q1_DEV] of R49 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(37.5251 mm, 104.2026 mm): Track [EXT5_PROT] on F.Cu, length 1.3496 mm
|
||||
@(42.2500 mm, 104.0000 mm): Pad 6 [EXT5_PROT] of U8 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(44.2500 mm, 59.0000 mm): Pad 24 [FTDI_B_TDO_SRC] of U2 on F.Cu
|
||||
@(96.5100 mm, 70.0000 mm): Pad 2 [FTDI_B_TDO_SRC] of R73 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(47.0000 mm, 56.7500 mm): Pad 32 [FTDI_C_TXD_SRC] of U2 on F.Cu
|
||||
@(62.8625 mm, 54.8250 mm): Pad 15 [FTDI_C_TXD_SRC] of U29 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(47.0000 mm, 51.7500 mm): Pad 42 [FTDI_D_TXD_SRC] of U2 on F.Cu
|
||||
@(62.8625 mm, 53.5250 mm): Pad 17 [FTDI_D_TXD_SRC] of U29 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(105.6000 mm, 65.6000 mm): Track [VCC3V3] on F.Cu, length 0.5657 mm
|
||||
@(108.8000 mm, 64.0000 mm): Track [VCC3V3] on F.Cu, length 0.5657 mm
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(110.4000 mm, 67.2000 mm): Pad F15 [VCC3V3] of U1 on F.Cu
|
||||
@(112.0000 mm, 75.2000 mm): Pad T17 [VCC3V3] of U1 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(110.4000 mm, 67.2000 mm): Track [VCC3V3] on F.Cu, length 0.5657 mm
|
||||
@(108.8000 mm, 64.0000 mm): Track [VCC3V3] on F.Cu, length 0.5657 mm
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(112.8000 mm, 76.8000 mm): Track [VCC3V3] on F.Cu, length 0.5657 mm
|
||||
@(112.0000 mm, 75.2000 mm): Track [VCC3V3] on F.Cu, length 0.5657 mm
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(113.2000 mm, 77.2000 mm): Via [VCC3V3] on F.Cu - B.Cu
|
||||
@(119.3969 mm, 80.9333 mm): Track [VCC3V3] on F.Cu, length 0.3913 mm
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(111.2000 mm, 67.2000 mm): Pad F16 [MAX_SCLK] of U1 on F.Cu
|
||||
@(120.9900 mm, 65.5000 mm): Pad 1 [MAX_SCLK] of R51 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(32.5100 mm, 58.0000 mm): Pad 2 [FTDI_OSCI] of R67 on F.Cu
|
||||
@(39.0000 mm, 52.7500 mm): Pad 3 [FTDI_OSCI] of U2 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(39.0000 mm, 55.7500 mm): Pad 9 [FTDI_VPLL] of U2 on F.Cu
|
||||
@(47.7170 mm, 58.2000 mm): Track [FTDI_VPLL] on L5_SIG, length 10.0820 mm
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(106.4000 mm, 68.0000 mm): Pad G10 [HARD_TCK] of U1 on F.Cu
|
||||
@(96.9700 mm, 65.7400 mm): Track [HARD_TCK] on F.Cu, length 0.6505 mm
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(107.2000 mm, 67.2000 mm): Pad F11 [MAX_LD] of U1 on F.Cu
|
||||
@(160.5000 mm, 46.9900 mm): Pad 2 [MAX_LD] of R50 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(83.0800 mm, 24.0000 mm): PTH pad 3 [PMOD1_3] of JPMOD1
|
||||
@(108.8000 mm, 63.2000 mm): Pad A13 [PMOD1_3] of U1 on F.Cu
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(112.0000 mm, 63.2000 mm): Pad A17 [PMOD3_8] of U1 on F.Cu
|
||||
@(116.5400 mm, 26.5400 mm): PTH pad 8 [PMOD3_8] of JPMOD3
|
||||
[unconnected_items]: Missing connection between items
|
||||
Local override; error
|
||||
@(111.2000 mm, 68.0000 mm): Pad G16 [MAX_SDATA] of U1 on F.Cu
|
||||
@(120.9900 mm, 67.9000 mm): Pad 1 [MAX_SDATA] of R53 on F.Cu
|
||||
** Found 0 unconnected pads **
|
||||
|
||||
** Found 0 Footprint errors **
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
ERC report (2026-08-16T01:41:08, Encoding UTF8)
|
||||
Report includes: Errors, Warnings
|
||||
ERC report (2026-08-21T00:59:47, Encoding UTF8)
|
||||
Report includes: Errors, Warnings, Exclusions
|
||||
|
||||
***** Sheet /
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Comment,Designator,Footprint,LCSC Part #,Manufacturer,Manufacturer Part Number,Quantity,Assembly Type,DNP
|
||||
100nF,C1,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
|
||||
100nF,"C1,C129",Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,2,SMT,no
|
||||
47uF,"C10,C11",Capacitor_SMD:C_1210_3225Metric,,Murata,GRM32ER70J476ME19L,2,SMT,no
|
||||
100nF,C100,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R71A104KA01D,1,SMT,no
|
||||
1uF,C101,Capacitor_SMD:C_0402_1005Metric,,Murata,GRM155R60J105KE19D,1,SMT,no
|
||||
@@ -85,6 +85,7 @@ GPS L1 SMA,J2,Connector_Coaxial:SMA_Amphenol_132289_EdgeMount,,Amphenol RF,13228
|
||||
EXT_5V,J3,"TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal",,Phoenix Contact,1935161,1,THT,no
|
||||
EXT RESET_N,J4,Connector_JST:JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal,,JST,SM02B-SRSS-TB(LF)(SN),1,SMT,no
|
||||
ANT BIAS OFF/3V3/5V,J5,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,,Wuerth Elektronik,61300311121,1,THT,no
|
||||
USB-C power input,J7,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,,GCT,USB4105-GF-A-120,1,SMT,no
|
||||
PMOD 3.3 V,"JPMOD1,JPMOD2",board:Digilent_PMOD_2x6_P2.54mm,,Amphenol ICC,67997-412HLF,2,THT,no
|
||||
PMOD 1.8 V,"JPMOD3,JPMOD4",board:Digilent_PMOD_2x6_P2.54mm,,Amphenol ICC,67997-412HLF,2,THT,no
|
||||
100nH,L1,board:Coilcraft_XEL4030,,Coilcraft,XEL4030-101MEC,1,SMT,no
|
||||
@@ -134,7 +135,7 @@ MMBT3904,Q1,Package_TO_SOT_SMD:SOT-23,,onsemi,MMBT3904LT1G,1,SMT,no
|
||||
100K,R55,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07100KL,1,SMT,no
|
||||
33R,R56,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0733RL,1,SMT,no
|
||||
22R,"R57,R58,R59",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0722RL,3,SMT,no
|
||||
900K,R6,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07909KL,1,SMT,no
|
||||
900K,"R6,R107",Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-07909KL,2,SMT,no
|
||||
22R,R60,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0722RL,1,SMT,no
|
||||
10K,R61,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0710KL,1,SMT,no
|
||||
27R,R62,Resistor_SMD:R_0402_1005Metric,,Yageo,RC0402FR-0727RL,1,SMT,no
|
||||
@@ -204,6 +205,7 @@ SN74LVC1G07,U31,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G07DBVR,1
|
||||
SN74LVC1G07,U32,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G07DBVR,1,SMT,no
|
||||
SN74LVC1G07,U33,Package_TO_SOT_SMD:SOT-23-5,,Texas Instruments,SN74LVC1G07DBVR,1,SMT,no
|
||||
SN74LVC08A,U34,Package_SO:TSSOP-14_4.4x5mm_P0.65mm,,Texas Instruments,SN74LVC08APWR,1,SMT,no
|
||||
TUSB320LAI,U35,Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,,Texas Instruments,TUSB320LAIRSW(R),1,SMT,no
|
||||
TUSB320LAI,U5,Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,,Texas Instruments,TUSB320LAIRSW(R),1,SMT,no
|
||||
TPD2EUSB30A,U6,Package_TO_SOT_SMD:Texas_DRT-3,,Texas Instruments,TPD2EUSB30ADRTR,1,SMT,no
|
||||
TPS259470A,"U7,U8",board:Texas_RPW0010A_QFN10,,Texas Instruments,TPS259470ARPWR,2,SMT,no
|
||||
|
||||
|
@@ -0,0 +1,21 @@
|
||||
Board: hardware/board_routed.kicad_pcb
|
||||
Unconnected endpoints reported by connectivity: 0
|
||||
Tracks: 3065 Vias: 1018
|
||||
|
||||
Track segments per layer:
|
||||
F.Cu 1746
|
||||
L6_SIG 481
|
||||
L5_SIG 390
|
||||
L3_SIG 387
|
||||
B.Cu 61
|
||||
|
||||
Track width used per net class (mm: segments):
|
||||
BGA_ESCAPE 0.1: 423
|
||||
CLOCK 0.1: 17, 0.15: 145
|
||||
Default 0.1: 37, 0.12: 1373, 0.15: 5
|
||||
POWER 0.1: 79, 0.12: 4, 0.15: 193, 0.163: 18, 0.195: 1, 0.2: 4, 0.22: 12, 0.227: 3, 0.25: 247, 0.26: 6, 0.3: 327, 0.35: 1, 0.4: 103, 0.45: 2, 0.5: 2, 0.55: 10, 0.6: 4, 0.7: 2, 0.8: 5, 1.0: 1, 1.2: 4, 1.5: 2
|
||||
RF50_CPWG 0.164: 11
|
||||
USB90_DIFF 0.135: 24
|
||||
|
||||
Nets still split into more than one copper group:
|
||||
none - every net is one connected group
|
||||
+91
-11
@@ -151,17 +151,35 @@ kartta pass başına yaklaşık dört kat yavaş çalışır.
|
||||
Buradaki alan sayısı doğrudan yerel güç aşamasının ne kadar bakır bıraktığına
|
||||
bağlıdır: via cloud'lar temizlendikten sonra 4146 keepout 2541'e düştü.
|
||||
|
||||
Bundled Freerouting 2.3.0 build'i KiCad 10 DSN clearance değerlerini doğrudan
|
||||
doğru ölçekte okur; clearance değerleri ölçeklenmez. Bu sürüm çok-thread route
|
||||
optimizasyonunun clearance ihlali üretebildiğini kendi logunda bildirir, bu
|
||||
nedenle `-mt 1` kullanılır ve sonuç `.ses` olarak kaydedilir.
|
||||
Bu aşamanın autorouter'ı hâlâ **Freerouting 2.3.0**'dır (aşağıda). KiCad 10 DSN
|
||||
clearance değerlerini doğru ölçekte okur; `-mt 1` ile çalıştırılır (çok-thread
|
||||
optimizasyon clearance ihlali üretebiliyor).
|
||||
|
||||
`hardware/power_routes.json` ve `hardware/critical_routes.json` el çizimi
|
||||
geometriyi veri olarak tutar (bkz. `hardware/routes_schema.md`); tek seferlik
|
||||
üretim: `/usr/bin/python3 scripts/_extract_fixed_routes.py`.
|
||||
|
||||
> Bu repoda bir zamanlar `router/` altında bağımsız bir C++ autorouter +
|
||||
> Qt GUI (`pcbrouter`) vardı. Yoğun 8 katmanlı sinyal aşamasında Freerouting
|
||||
> kadar tamamlamadığı için kartın routing akışında hiç kullanılmadı ve
|
||||
> 2026-09-01'de repodan çıkarıldı (`../pcbrouter-cpp-20260901.tar.gz` olarak
|
||||
> arşivlendi). Sinyal aşaması Freerouting 2.3.0, kalan bağlantılar
|
||||
> `close_remaining.py` ile kapatılır.
|
||||
|
||||
```bash
|
||||
.tools/freerouting-2.3.0/app/freerouting-2.3.0-linux-x64/bin/freerouting \
|
||||
-de outputs/signal_stage.dsn -do outputs/signal_stage.ses \
|
||||
-mp 60 -mt 1 -us Greedy -is prioritized
|
||||
-de outputs/signal_stage.dsn -do outputs/signal_stage_pass4.ses \
|
||||
-mp 4 -mt 1 -us Greedy -is prioritized
|
||||
```
|
||||
|
||||
Bu tasarımda Freerouting'in 20-25 bağlantıda plato yapması beklenen durumdur;
|
||||
onu sıfıra ulaşana kadar açık bırakmak session'ın hiç yazılmamasına yol açar.
|
||||
`-mp 4` global yoğun rotayı sınırlar ve kalan bağlantılar varken de geçerli SES
|
||||
yazar. İnce BGA/FTDI çıkışları, mevcut dogbone ve track uçlarını anchor olarak
|
||||
kullanan KiCad-side finisher tarafından sonraki adımda tamamlanır. Böylece SES
|
||||
kaydı için sıfır unrouted önkoşulu yoktur; sıfır bağlantı ve sıfır DRC yalnızca
|
||||
son KiCad kontrolünün kabul ölçütüdür.
|
||||
|
||||
RF, USB ve güç converter loopları otomatik sonuca bırakılmaz. Bu netler DSN'de
|
||||
hiç yoktur; yerlerini `generate_pcb.py` içindeki `TEMP_` rule area'ları tutar.
|
||||
`TEMP_*_BELOW` alanları RF ve USB altındaki referans/routing katmanlarını,
|
||||
@@ -173,19 +191,79 @@ kurallarıyla route edilir ve finalde ayrıca incelenir.
|
||||
|
||||
```bash
|
||||
/usr/bin/python3 scripts/finalize_routing.py \
|
||||
outputs/signal_stage.ses \
|
||||
outputs/signal_stage_pass4.ses \
|
||||
--base hardware/board_power_local.kicad_pcb \
|
||||
--output hardware/board_routed.kicad_pcb
|
||||
--output hardware/board_routed.kicad_pcb \
|
||||
--finish-nets auto
|
||||
```
|
||||
|
||||
Bu işlem Freerouter'ın RF ve USB üzerindeki copperını kaldırır, geçici rule
|
||||
area'ları siler, denetlenmiş RF/USB geometrisini ekler ve RF GND via fence'i
|
||||
kurar. Ardından koridorlar boşaldığı için `stitch_plane_pads` ve
|
||||
`route_local_power` bir kez daha çalıştırılır; bu, RF/USB bölgesindeki güç
|
||||
pad'lerinin plane'e ulaşabildiği tek andır. Son olarak plane'lerde island
|
||||
temizliği açılır ve zone'lar doldurulur.
|
||||
pad'lerinin plane'e ulaşabildiği tek andır. Kalan CLOCK, BGA_ESCAPE, Default ve
|
||||
yalnız düşük-akım yerel POWER netleri `finish_signal_routes.py` ile kapatılır;
|
||||
5-V giriş yolları ile ana FPGA rayları dar fallback route'a kesinlikle verilmez.
|
||||
Son olarak dangling copper temizlenir, plane'lerde island temizliği açılır ve
|
||||
zone'lar doldurulur.
|
||||
|
||||
### 7. Final kontroller
|
||||
### 7. Kalan bağlantıları kapat
|
||||
|
||||
```bash
|
||||
/usr/bin/python3 scripts/close_remaining.py \
|
||||
hardware/board_routed.kicad_pcb --deadline 60 --ripup-depth 2
|
||||
```
|
||||
|
||||
Freerouting ve yerel tamamlama adımlarından sonra kalan her açık bağlantıyı tek
|
||||
bir çok katmanlı maze router ile kapatır. Bu adımın yerini aldığı eski
|
||||
artık-bağlantı scriptlerinin sabit bir şekli vardı: A pad'inin yanına via, tek
|
||||
bir katmanda A*, B pad'inin yanına via. Bu şekil, dört dogbone noktası da dolu
|
||||
olan bir 0.8 mm BGA balını kaçıramaz ve sinyal hatlarının adalara böldüğü bir
|
||||
güç pour'unu köprüleyemez. Bu kartta kalan başarısızlıklar tam olarak bunlardı,
|
||||
bu yüzden o scriptler kaldırıldı.
|
||||
|
||||
`close_remaining.py`:
|
||||
|
||||
- Beş route edilebilir katmanın hepsinde `(x, y, katman)` üzerinde 0.1 mm
|
||||
adımla arar; via'nın yasal olarak sığdığı her yerde katman değiştirir.
|
||||
- Başlangıç ve hedef, birleştirilen iki grubun **bütün** bakırıdır (pad, track,
|
||||
via); tek bir pad değil.
|
||||
- Clearance'ı gerçek pad/track/via geometrisinden, gerçek net-class
|
||||
değerleriyle hesaplar.
|
||||
- Bakırı U1 courtyard'ı içinde 0.10 mm'ye daraltır (iki 0.8 mm land arasından
|
||||
geçen tek genişlik), dışarıda net-class genişliğini kullanır.
|
||||
- Yabancı bir güç pour'unun içine girmez; böylece yeni bir hat bir güç adasını
|
||||
ikiye bölemez.
|
||||
- Sığmayan bir bağlantı için autorouter bakırını **geri alınabilir şekilde**
|
||||
söker: hattı geçirir, yerinden ettiği netleri tekrar route eder, biri geri
|
||||
konamazsa her şeyi eski haline döndürür. Rip-up kartı asla bulduğundan daha
|
||||
kötü bırakmaz.
|
||||
|
||||
Eklenen her şey kilitlidir. Sonrasında zone'lar doldurulur ve dangling bakır
|
||||
temizlenir.
|
||||
|
||||
#### Bu adımın gerektirdiği iki kural değişikliği
|
||||
|
||||
**1. `Ti375 escape field copper clearance` (yeni, `board.kicad_dru`).**
|
||||
0.8 mm ball pitch, iki komşu 0.45 mm dogbone via arasında 0.35 mm'lik bir
|
||||
kanal bırakır. 0.10 mm'lik bir hat bu kanala escape alanının 0.10 mm bakır
|
||||
minimumunda sığar, CLOCK sınıfının 0.15 mm'sinde sığmaz (0.10 + 2x0.15 = 0.40
|
||||
> 0.35). Bu yüzden `HARD_TCK` ve `MAX_SCLK` paketten hiç çıkarılamıyordu. Yeni
|
||||
kural, **her iki nesne de** U1 courtyard'ının içindeyken clearance'ı bu alanın
|
||||
geri kalanının zaten kullandığı 0.10 mm'ye indirir. Clock trunk, U1
|
||||
courtyard'ından çıkar çıkmaz 0.15 mm'sine geri döner.
|
||||
|
||||
**2. `RF_NO_DIGITAL` artık RF hattının koridoru kadar.**
|
||||
Alan (152, 36)-(174.5, **49.5**) dikdörtgeniydi; RF bakırı ise y <= 42.6'da
|
||||
kalıyor. Yani alan, RF hattının 7 mm güneyine kadar uzanıyor ve MAX2771'in
|
||||
bütün dijital pin sıralarını (y = 44.5 .. 47.4) içine alıyordu. Sonuç: U21'in
|
||||
her dijital çıkışı yalnız F.Cu'dan kaçmak zorundaydı ve sığmıyordu. Alan
|
||||
(152, 36)-(174.5, **43.7**) yapıldı; bu, `generate_pcb.py`'nin `TEMP_RF_LINE`
|
||||
olarak zaten ayırdığı koridorun aynısıdır ve RF bakırını 1.1 mm açıkla geçer.
|
||||
RF dönüş yolu zaten bu alan tarafından değil, üzerinde hiç route edilmeyen
|
||||
L2/L7 GND plane'leri tarafından garanti edilir.
|
||||
|
||||
### 8. Final kontroller
|
||||
|
||||
```bash
|
||||
kicad-cli pcb drc --severity-all --schematic-parity --refill-zones \
|
||||
@@ -221,4 +299,6 @@ loopları, return path ve test-point erişimi görsel olarak da incelenmelidir.
|
||||
| `export_routing_stage.py` | Seçili net-class için DSN üretimi |
|
||||
| `prepare_freerouting_dsn.py` | Yalnız doğrulanmış farklı router build'leri için opsiyonel DSN clearance ölçekleme |
|
||||
| `finalize_routing.py` | SES importu ve denetlenmiş RF/USB geometrisi |
|
||||
| `finish_signal_routes.py` | Global router'ın bıraktığı yerel bağlantıları gerçek KiCad obstacle modeliyle tamamlar |
|
||||
| `close_remaining.py` | Kalan bütün açık bağlantıları çok katmanlı maze + geri alınabilir rip-up ile kapatır |
|
||||
| `report_routing.py` | Routed kartta eksik bağlantı, hat genişliği ve katman dağılımı raporu |
|
||||
|
||||
@@ -0,0 +1,154 @@
|
||||
#!/usr/bin/env python3
|
||||
"""One-time generator: capture the hand-drawn geometry from route_power_stage.py
|
||||
and finalize_routing.py into hardware/power_routes.json and
|
||||
hardware/critical_routes.json, which the project-independent `pcbrouter fixed`
|
||||
loader consumes.
|
||||
|
||||
This is a development tool, not part of the routing flow. It uses pcbnew only to
|
||||
resolve the pad anchors the scripts reference; the emitted JSON is plain data.
|
||||
The JSON files are already committed; you only need this to regenerate them after
|
||||
changing route_power_stage.py / finalize_routing.py.
|
||||
|
||||
It reads the intermediate boards board_prerouted.kicad_pcb and
|
||||
board_power_local.kicad_pcb, which are git-ignored pipeline artifacts. If they
|
||||
are not present, regenerate them first by running steps 1-4 of scripts/README.md
|
||||
(preroute_bga -> route_power_stage -> stitch_plane_pads -> route_local_power).
|
||||
|
||||
/usr/bin/python3 scripts/_extract_fixed_routes.py
|
||||
"""
|
||||
from __future__ import annotations
|
||||
|
||||
import json
|
||||
from pathlib import Path
|
||||
|
||||
import pcbnew
|
||||
|
||||
ROOT = Path(__file__).resolve().parents[1]
|
||||
|
||||
|
||||
def mm(v: int) -> float:
|
||||
return round(pcbnew.ToMM(v), 4)
|
||||
|
||||
|
||||
class Capture:
|
||||
def __init__(self) -> None:
|
||||
self.tracks: list[dict] = []
|
||||
self.vias: list[dict] = []
|
||||
|
||||
def track(self, net, a, b, width, layer_name):
|
||||
if a == b:
|
||||
return
|
||||
self.tracks.append({
|
||||
"net": net, "layer": layer_name, "width": round(width, 4),
|
||||
"points": [[round(a[0], 4), round(a[1], 4)], [round(b[0], 4), round(b[1], 4)]],
|
||||
})
|
||||
|
||||
def via(self, net, x, y, dia=0.45, drill=0.225):
|
||||
self.vias.append({"net": net, "at": [round(x, 4), round(y, 4)],
|
||||
"diameter": round(dia, 4), "drill": round(drill, 4)})
|
||||
|
||||
def as_json(self) -> dict:
|
||||
# merge consecutive same-net/same-layer/same-width segments into polylines
|
||||
merged: list[dict] = []
|
||||
for t in self.tracks:
|
||||
if (merged and merged[-1]["net"] == t["net"]
|
||||
and merged[-1]["layer"] == t["layer"]
|
||||
and abs(merged[-1]["width"] - t["width"]) < 1e-6
|
||||
and merged[-1]["points"][-1] == t["points"][0]):
|
||||
merged[-1]["points"].append(t["points"][1])
|
||||
else:
|
||||
merged.append({"net": t["net"], "layer": t["layer"],
|
||||
"width": t["width"], "points": list(t["points"])})
|
||||
return {"tracks": merged, "vias": self.vias}
|
||||
|
||||
|
||||
def layer_name(board, layer_id):
|
||||
return board.GetLayerName(layer_id)
|
||||
|
||||
|
||||
def patch_power_stage(cap: Capture, board):
|
||||
import route_power_stage as rps
|
||||
|
||||
def add_track(b, net, start, end, width, layer=pcbnew.F_Cu):
|
||||
cap.track(net, start, end, width, layer_name(board, layer))
|
||||
|
||||
def add_via(b, net, x, y, diameter=0.70, drill=0.35):
|
||||
cap.via(net, x, y, diameter, drill)
|
||||
|
||||
rps.add_track = add_track
|
||||
rps.add_via = add_via
|
||||
rps.add_path = lambda b, net, pts, w, layer=pcbnew.F_Cu: [
|
||||
add_track(b, net, s, e, w, layer) for s, e in zip(pts, pts[1:])
|
||||
]
|
||||
|
||||
|
||||
def patch_finalize(cap: Capture, board):
|
||||
import finalize_routing as fr
|
||||
|
||||
def add_segment(b, net, start, end, width, layer=pcbnew.F_Cu, locked=True):
|
||||
cap.track(net, start, end, width, layer_name(board, layer))
|
||||
|
||||
def add_polyline(b, net, verts, width, layer=pcbnew.F_Cu):
|
||||
for s, e in zip(verts, verts[1:]):
|
||||
add_segment(b, net, s, e, width, layer)
|
||||
|
||||
def add_via(b, net, position, diameter=0.45, drill=0.225):
|
||||
cap.via(net, position[0], position[1], diameter, drill)
|
||||
|
||||
fr.add_segment = add_segment
|
||||
fr.add_polyline = add_polyline
|
||||
fr.add_via = add_via
|
||||
|
||||
|
||||
def main() -> None:
|
||||
for stem in ("board_prerouted", "board_power_local"):
|
||||
if not (ROOT / "hardware" / f"{stem}.kicad_pcb").exists():
|
||||
raise SystemExit(
|
||||
f"hardware/{stem}.kicad_pcb missing - regenerate the pipeline "
|
||||
"intermediates first (steps 1-4 of scripts/README.md).")
|
||||
|
||||
# -- power routes -------------------------------------------------------
|
||||
board = pcbnew.LoadBoard(str(ROOT / "hardware" / "board_prerouted.kicad_pcb"))
|
||||
cap = Capture()
|
||||
patch_power_stage(cap, board)
|
||||
import route_power_stage as rps
|
||||
rps.route_core_buck(board)
|
||||
rps.route_small_buck(board, regulator="U14", inductor="L2",
|
||||
input_caps=("C26", "C27"), output_caps=("C28", "C29"),
|
||||
sw_net="BUCK1V8_SW", out_net="VCC1V8",
|
||||
input_x=112.98, plane_via_x=120.105)
|
||||
rps.route_small_buck(board, regulator="U15", inductor="L3",
|
||||
input_caps=("C30", "C31"), output_caps=("C32", "C33"),
|
||||
sw_net="BUCK3V3_SW", out_net="VCC3V3",
|
||||
input_x=127.98, plane_via_x=135.105)
|
||||
(ROOT / "hardware" / "power_routes.json").write_text(
|
||||
json.dumps(cap.as_json(), indent=1) + "\n")
|
||||
print(f"power_routes.json: {len(cap.as_json()['tracks'])} polylines, {len(cap.vias)} vias")
|
||||
|
||||
# -- critical (RF / USB) routes + rule areas --------------------------
|
||||
board = pcbnew.LoadBoard(str(ROOT / "hardware" / "board_power_local.kicad_pcb"))
|
||||
cap = Capture()
|
||||
patch_finalize(cap, board)
|
||||
import finalize_routing as fr
|
||||
fr.route_rf(board)
|
||||
fr.route_usb(board)
|
||||
data = cap.as_json()
|
||||
data["rule_areas"] = [
|
||||
{"name": "USB_ESD_BREAKOUT", "layers": ["F.Cu"], "rect": [29.90, 50.70, 32.10, 53.10]},
|
||||
{"name": "RF_NO_DIGITAL", "layers": ["B.Cu", "In2.Cu", "In4.Cu", "In5.Cu"],
|
||||
"rect": [152.00, 36.00, 174.50, 43.70]},
|
||||
]
|
||||
fence = [[x, 38.7] for x in range(153, 174, 2)] + [[x, 45.0] for x in range(161, 174, 2)]
|
||||
data["ground_zones"] = [{
|
||||
"net": "GND", "layer": "F.Cu", "clearance": 0.20, "min_thickness": 0.10,
|
||||
"priority": 100,
|
||||
"outline": [[152.0, 36.0], [174.5, 36.0], [174.5, 49.5], [152.0, 49.5]],
|
||||
"via_fence": fence,
|
||||
}]
|
||||
(ROOT / "hardware" / "critical_routes.json").write_text(json.dumps(data, indent=1) + "\n")
|
||||
print(f"critical_routes.json: {len(data['tracks'])} polylines, {len(cap.vias)} vias, "
|
||||
f"{len(data['rule_areas'])} rule areas, fence {len(fence)}")
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
File diff suppressed because it is too large
Load Diff
+48
-10
@@ -156,26 +156,30 @@ for name in ("REF_RES_4A", "REF_RES_4B", "REF_RES_4D", "REF_RES_2E", "REF_RES_2A
|
||||
r("10K", name, "GND", description="Efinix mandatory 10-kohm 1% reference resistor")
|
||||
|
||||
|
||||
# USB-C and sink role detection.
|
||||
# USB-C debug port (JTAG/UART only). This connector never sources SYS5: its
|
||||
# VBUS pins only feed local presence-sensing dividers, so a host attached here
|
||||
# can never be back-fed and dedicated USB power input J7 stays the only USB
|
||||
# source of board power. See J7 below for the power port and its TUSB320.
|
||||
add_ic("J1", "USB-C USB2 sink", "USB4105-GF-A-120", "GCT",
|
||||
"Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal", [
|
||||
p("A1", "GND", "GND"), p("A4", "VBUS", "VBUS_RAW"), p("A5", "CC1", "USB_CC1"),
|
||||
p("A1", "GND", "GND"), p("A4", "VBUS", "DBG_VBUS_RAW"), p("A5", "CC1", "USB_CC1"),
|
||||
p("A6", "D+", "USB_D_P"), p("A7", "D-", "USB_D_N"), p("A8", "SBU1", None),
|
||||
p("A9", "VBUS", "VBUS_RAW"), p("A12", "GND", "GND"),
|
||||
p("B1", "GND", "GND"), p("B4", "VBUS", "VBUS_RAW"), p("B5", "CC2", "USB_CC2"),
|
||||
p("A9", "VBUS", "DBG_VBUS_RAW"), p("A12", "GND", "GND"),
|
||||
p("B1", "GND", "GND"), p("B4", "VBUS", "DBG_VBUS_RAW"), p("B5", "CC2", "USB_CC2"),
|
||||
p("B6", "D+", "USB_D_P"), p("B7", "D-", "USB_D_N"), p("B8", "SBU2", None),
|
||||
p("B9", "VBUS", "VBUS_RAW"), p("B12", "GND", "GND"), p("SH", "SHIELD", "USB_SHIELD")],
|
||||
"USB 2.0 Type-C receptacle, UFP/sink")
|
||||
p("B9", "VBUS", "DBG_VBUS_RAW"), p("B12", "GND", "GND"), p("SH", "SHIELD", "USB_SHIELD")],
|
||||
"USB 2.0 Type-C receptacle, UFP/sink, debug data only")
|
||||
add_ic("U5", "TUSB320LAI", "TUSB320LAIRSW(R)", "Texas Instruments",
|
||||
"Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm", [
|
||||
p(1, "CC1", "USB_CC1", "bidirectional"), p(2, "CC2", "USB_CC2", "bidirectional"),
|
||||
p(3, "PORT", "GND", "input"), p(4, "VBUS_DET", "USB_VBUS_DET", "input"),
|
||||
p(5, "ADDR", None), p(6, "OUT3", None, "output"),
|
||||
p(7, "OUT1", "TUSB_OUT1", "output"), p(8, "OUT2", "TUSB_OUT2", "output"),
|
||||
p(7, "OUT1", None, "output"), p(8, "OUT2", None, "output"),
|
||||
p(9, "ID", None, "output"), p(10, "GND", "GND", "power_in"),
|
||||
p(11, "EN_N", "GND", "input"), p(12, "VDD", "VCC3V3_AUX", "power_in")],
|
||||
"USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2")
|
||||
r("900K", "VBUS_RAW", "USB_VBUS_DET", description="TUSB320 VBUS_DET current limiter")
|
||||
"USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2; "
|
||||
"current-advertisement outputs unused since this port never sources SYS5")
|
||||
r("900K", "DBG_VBUS_RAW", "USB_VBUS_DET", description="TUSB320 VBUS_DET current limiter")
|
||||
r("10K", "VCC3V3_AUX", "TUSB_OUT1", description="TUSB320 open-drain OUT1 pull-up")
|
||||
r("10K", "VCC3V3_AUX", "TUSB_OUT2", description="TUSB320 open-drain OUT2 pull-up")
|
||||
c("100nF", "VCC3V3_AUX", "GND", description="TUSB320 local bypass")
|
||||
@@ -546,7 +550,7 @@ add_ic("U2", "FT4232H-56Q", "FT4232H-56Q-REEL", "FTDI", "board:FTDI_VQFN56_EP5p9
|
||||
r("27R", "USB_D_P", "FTDI_D_P", description="FTDI USB D+ series termination")
|
||||
r("27R", "USB_D_N", "FTDI_D_N", description="FTDI USB D- series termination")
|
||||
r("12K", "FTDI_REF", "GND", description="FT4232H USB PHY reference resistor, 1%")
|
||||
r("4.7K", "VBUS_RAW", "FTDI_RESET_N", description="Self-powered VBUS-present reset divider top")
|
||||
r("4.7K", "DBG_VBUS_RAW", "FTDI_RESET_N", description="Self-powered VBUS-present reset divider top")
|
||||
r("10K", "FTDI_RESET_N", "GND", description="Self-powered VBUS-present reset divider bottom")
|
||||
for _ in range(2):
|
||||
c("100nF", "VCC3V3_AUX", "GND", description="FT4232H VCCIO/VREGIN bypass")
|
||||
@@ -718,6 +722,40 @@ add_ic("D2", "RESET ESD", "ESD5Z3.3T1G", "onsemi", "Diode_SMD:D_SOD-523", [
|
||||
"External-reset connector ESD clamp")
|
||||
|
||||
|
||||
# Dedicated USB-C power input, physically and electrically separate from the
|
||||
# J1 debug/JTAG/UART port. Its VBUS feeds eFuse U7 (unchanged: U7 already
|
||||
# reads net "VBUS_RAW", which now belongs to this connector instead of J1) so
|
||||
# it goes through the same reverse-blocking protection as before and arrives
|
||||
# at the same TPS2121 IN1 input. U9 keeps external EXT5_PROT (J3) as the
|
||||
# higher-priority source, so external power and this USB-C power input can
|
||||
# never feed SYS5 at the same time. D+/D-/SBU are power-only and left
|
||||
# unconnected; the shield ties to the same USB_SHIELD net as J1.
|
||||
add_ic("J7", "USB-C power input", "USB4105-GF-A-120", "GCT",
|
||||
"Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal", [
|
||||
p("A1", "GND", "GND"), p("A4", "VBUS", "VBUS_RAW"), p("A5", "CC1", "PWR_CC1"),
|
||||
p("A6", "D+", None), p("A7", "D-", None), p("A8", "SBU1", None),
|
||||
p("A9", "VBUS", "VBUS_RAW"), p("A12", "GND", "GND"),
|
||||
p("B1", "GND", "GND"), p("B4", "VBUS", "VBUS_RAW"), p("B5", "CC2", "PWR_CC2"),
|
||||
p("B6", "D+", None), p("B7", "D-", None), p("B8", "SBU2", None),
|
||||
p("B9", "VBUS", "VBUS_RAW"), p("B12", "GND", "GND"), p("SH", "SHIELD", "USB_SHIELD")],
|
||||
"USB 2.0 Type-C receptacle, UFP/sink, power input only")
|
||||
add_ic("U35", "TUSB320LAI", "TUSB320LAIRSW(R)", "Texas Instruments",
|
||||
"Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm", [
|
||||
p(1, "CC1", "PWR_CC1", "bidirectional"), p(2, "CC2", "PWR_CC2", "bidirectional"),
|
||||
p(3, "PORT", "GND", "input"), p(4, "VBUS_DET", "PWR_USB_VBUS_DET", "input"),
|
||||
p(5, "ADDR", None), p(6, "OUT3", None, "output"),
|
||||
p(7, "OUT1", "TUSB_OUT1", "output"), p(8, "OUT2", "TUSB_OUT2", "output"),
|
||||
p(9, "ID", None, "output"), p(10, "GND", "GND", "power_in"),
|
||||
p(11, "EN_N", "GND", "input"), p(12, "VDD", "VCC3V3_AUX", "power_in")],
|
||||
"USB Type-C port controller in UFP GPIO mode for the power input; "
|
||||
"integrated Rd on CC1/CC2; OUT1/OUT2 3-A advertisement drives U10/U11 MAIN_EN gating")
|
||||
# TUSB_OUT1/TUSB_OUT2 pull-ups already exist beside U5 (net names are reused,
|
||||
# not the physical position); adding a second pair here would halve their
|
||||
# effective value instead of moving them.
|
||||
r("900K", "VBUS_RAW", "PWR_USB_VBUS_DET", description="TUSB320 VBUS_DET current limiter")
|
||||
c("100nF", "VCC3V3_AUX", "GND", description="TUSB320 local bypass")
|
||||
|
||||
|
||||
def validate() -> None:
|
||||
refs = [x.ref for x in components]
|
||||
assert len(refs) == len(set(refs))
|
||||
|
||||
@@ -15,6 +15,7 @@ from pathlib import Path
|
||||
|
||||
import pcbnew
|
||||
|
||||
import finish_signal_routes
|
||||
import route_local_power
|
||||
import stitch_plane_pads
|
||||
|
||||
@@ -35,6 +36,20 @@ def point(x: float, y: float) -> pcbnew.VECTOR2I:
|
||||
return pcbnew.VECTOR2I_MM(x, y)
|
||||
|
||||
|
||||
def remove(board: pcbnew.BOARD, item) -> None:
|
||||
"""Remove and disown a board item.
|
||||
|
||||
pcbnew's BOARD.Remove() does not clear the SWIG "thisown" flag, so the
|
||||
Python wrapper still believes it owns the now-freed C++ object. Letting
|
||||
the garbage collector finalize it later double-frees that memory and
|
||||
corrupts the process (subsequent pcbnew calls start returning raw,
|
||||
unusable SwigPyObject instances instead of typed wrappers). Explicitly
|
||||
disowning the wrapper right after removal avoids that.
|
||||
"""
|
||||
board.Remove(item)
|
||||
item.thisown = False
|
||||
|
||||
|
||||
def footprint(board: pcbnew.BOARD, ref: str) -> pcbnew.FOOTPRINT:
|
||||
item = board.FindFootprintByReference(ref)
|
||||
if item is None:
|
||||
@@ -97,7 +112,7 @@ def add_via(board: pcbnew.BOARD, net_name: str, position: tuple[float, float],
|
||||
def remove_critical_routes(board: pcbnew.BOARD) -> int:
|
||||
doomed = [item for item in board.GetTracks() if item.GetNetname() in CRITICAL_NETS]
|
||||
for item in doomed:
|
||||
board.Remove(item)
|
||||
remove(board, item)
|
||||
return len(doomed)
|
||||
|
||||
|
||||
@@ -105,7 +120,7 @@ def remove_temporary_keepouts(board: pcbnew.BOARD) -> int:
|
||||
doomed = [zone for zone in board.Zones()
|
||||
if zone.GetIsRuleArea() and zone.GetZoneName().startswith("TEMP_")]
|
||||
for zone in doomed:
|
||||
board.Remove(zone)
|
||||
remove(board, zone)
|
||||
return len(doomed)
|
||||
|
||||
|
||||
@@ -215,6 +230,16 @@ def add_rf_ground(board: pcbnew.BOARD) -> None:
|
||||
outline.Append(point(x, y))
|
||||
board.Add(zone)
|
||||
|
||||
# J2 uses separate top- and bottom-side SMT lands with the same pad number.
|
||||
# The top lands overlap the RF ground zone, but a bottom land whose centre
|
||||
# is outside the outline cannot acquire a thermal from the board-wide B.Cu
|
||||
# pour. Start inside each 1.5-mm-wide land and stop far enough inboard for
|
||||
# the existing B.Cu pour to absorb the bond. At x=174.50 a 0.40-mm track
|
||||
# retains 0.30 mm to the x=175.00 routed edge (rule minimum 0.25 mm).
|
||||
for y in (37.75, 46.25):
|
||||
add_segment(board, "GND", (174.50, y), (173.50, y),
|
||||
0.40, pcbnew.B_Cu)
|
||||
|
||||
# Lambda/20 is about 9.5 mm at GPS L1 in FR-4. This 2-mm fence is much
|
||||
# tighter and also gives every local shunt/EP a short plane connection.
|
||||
fence = [(x, 38.7) for x in range(153, 174, 2)]
|
||||
@@ -267,6 +292,16 @@ NETCLASS_WIDTH = {"Default": 0.12, "BGA_ESCAPE": 0.10, "CLOCK": 0.15,
|
||||
MIN_TRACK_WIDTH = 0.10
|
||||
MIN_CLEARANCE = 0.10
|
||||
|
||||
# These local rails carry bias or IC-internal supply current and may safely use
|
||||
# the finisher's 0.25-mm POWER width. The 5-V input paths and FPGA rails are
|
||||
# deliberately absent: they must be completed by the plane/local-power stage
|
||||
# at their full width, never "made connected" with a signal-sized neck.
|
||||
FINE_POWER_NETS = {
|
||||
"FTDI_1V8", "FTDI_VPHY", "FTDI_VPLL",
|
||||
"IMU_3V3", "IMU_VREGA2", "IMU_VREGD",
|
||||
"ANT_BIAS_SEL", "ANT_BIAS_SW",
|
||||
}
|
||||
|
||||
|
||||
def normalize_imported_widths(board: pcbnew.BOARD) -> tuple[int, int]:
|
||||
"""Restore the net class width on copper the session came back too thin.
|
||||
@@ -304,7 +339,7 @@ def normalize_imported_widths(board: pcbnew.BOARD) -> tuple[int, int]:
|
||||
# further down rebuilds the connection at the proper width.
|
||||
doomed.append(item)
|
||||
for item in doomed:
|
||||
board.Remove(item)
|
||||
remove(board, item)
|
||||
return widened, len(doomed)
|
||||
|
||||
|
||||
@@ -330,7 +365,7 @@ def remove_dangling_copper(board: pcbnew.BOARD) -> tuple[int, int]:
|
||||
vias += 1
|
||||
else:
|
||||
tracks += 1
|
||||
board.Remove(item)
|
||||
remove(board, item)
|
||||
board.BuildConnectivity()
|
||||
return vias, tracks
|
||||
|
||||
@@ -372,13 +407,13 @@ def add_named_rule_areas(board: pcbnew.BOARD) -> None:
|
||||
under the RF path, which is exactly what an unrouted plane layer gives.
|
||||
"""
|
||||
below = pcbnew.LSET()
|
||||
for layer in (pcbnew.In2_Cu, pcbnew.In4_Cu, pcbnew.In5_Cu, pcbnew.B_Cu):
|
||||
for layer in (pcbnew.In2_Cu, pcbnew.In3_Cu, pcbnew.In4_Cu, pcbnew.In5_Cu, pcbnew.In7_Cu, pcbnew.In8_Cu, pcbnew.B_Cu):
|
||||
below.AddLayer(layer)
|
||||
top = pcbnew.LSET()
|
||||
top.AddLayer(pcbnew.F_Cu)
|
||||
areas = (
|
||||
("USB_ESD_BREAKOUT", (29.90, 50.70, 32.10, 53.10), top),
|
||||
("RF_NO_DIGITAL", (152.00, 36.00, 174.50, 49.50), below),
|
||||
("RF_NO_DIGITAL", (152.00, 36.00, 174.50, 43.70), below),
|
||||
)
|
||||
for name, bounds, layers in areas:
|
||||
x0, y0, x1, y1 = bounds
|
||||
@@ -415,6 +450,12 @@ def main() -> None:
|
||||
parser.add_argument("--base", type=Path, default=POWER_LOCAL,
|
||||
help="Board used to create the routed DSN")
|
||||
parser.add_argument("--output", type=Path, default=ROUTED)
|
||||
parser.add_argument(
|
||||
"--finish-nets", default="",
|
||||
help="Comma- or semicolon-separated residual nets to close with the "
|
||||
"fine local maze before dangling-copper cleanup; use 'auto' to "
|
||||
"consume the local router's exact unresolved-net result",
|
||||
)
|
||||
args = parser.parse_args()
|
||||
|
||||
board = pcbnew.LoadBoard(str(args.base))
|
||||
@@ -422,7 +463,12 @@ def main() -> None:
|
||||
raise RuntimeError(f"Could not import {args.session}")
|
||||
removed = remove_critical_routes(board)
|
||||
widened, dropped = normalize_imported_widths(board)
|
||||
stranded_vias, stranded_tracks = remove_dangling_copper(board)
|
||||
# Keep imported dogbones and dangling track ends until after the focused
|
||||
# finisher. They are useful legal anchors for the few connections the
|
||||
# global router leaves open. The old ordering deleted those anchors first
|
||||
# and then forced every residual route to find a brand-new via beside a
|
||||
# fine-pitch pad, which is exactly where there is no room.
|
||||
stranded_vias = stranded_tracks = 0
|
||||
removed_keepouts = remove_temporary_keepouts(board)
|
||||
route_rf(board)
|
||||
route_usb(board)
|
||||
@@ -437,7 +483,36 @@ def main() -> None:
|
||||
stitched, _unreachable = stitch_plane_pads.stitch(board)
|
||||
if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
|
||||
raise RuntimeError("Zone fill after final plane stitching failed")
|
||||
route_local_power.complete(board, signals=True)
|
||||
remaining = route_local_power.complete(board, signals=True)
|
||||
|
||||
requested = [name.strip()
|
||||
for name in args.finish_nets.replace(";", ",").split(",")
|
||||
if name.strip()]
|
||||
if requested == ["auto"]:
|
||||
candidates = []
|
||||
class_priority = {"CLOCK": 0, "BGA_ESCAPE": 1, "Default": 2}
|
||||
for name in remaining:
|
||||
net = board.FindNet(name)
|
||||
if net is None:
|
||||
continue
|
||||
klass = net.GetNetClassName()
|
||||
if klass in {"Default", "BGA_ESCAPE", "CLOCK"} or name in FINE_POWER_NETS:
|
||||
# Route the widest/most constrained clocks before ordinary
|
||||
# signals can spend their channels; local low-current rails
|
||||
# are last because their endpoints are confined to one IC.
|
||||
priority = class_priority.get(klass, 3)
|
||||
candidates.append((priority, name))
|
||||
finish_nets = [name for _priority, name in sorted(candidates)]
|
||||
print("Fine-maze residuals:", ", ".join(finish_nets) or "none")
|
||||
else:
|
||||
finish_nets = requested
|
||||
if finish_nets:
|
||||
board.BuildConnectivity()
|
||||
maze = finish_signal_routes.FineMaze(board)
|
||||
for net_name in finish_nets:
|
||||
if board.FindNet(net_name) is None:
|
||||
raise RuntimeError(f"Unknown --finish-nets entry: {net_name}")
|
||||
finish_signal_routes.finish_net(maze, net_name)
|
||||
|
||||
late_vias, late_tracks = remove_dangling_copper(board)
|
||||
cleaned = drop_plane_islands(board)
|
||||
|
||||
@@ -0,0 +1,403 @@
|
||||
#!/usr/bin/env python3
|
||||
"""Close a small, explicit set of residual PCB connections.
|
||||
|
||||
This is deliberately a *finisher*, not a full autorouter. It operates on the
|
||||
real KiCad board after the global Specctra route has been imported. For each
|
||||
requested net it finds the disconnected copper groups, chooses anchors from
|
||||
pads, existing track endpoints and vias, and runs a fine 3-D A* search through
|
||||
the board's actual copper obstacle model. Every committed segment and via is
|
||||
locked; KiCad DRC remains the acceptance test.
|
||||
|
||||
Unlike the older residual helpers, an endpoint does not need room for a new
|
||||
via. A route may leave a fine-pitch pad on its own copper layer, travel to a
|
||||
legal via site, and only then change layers. Existing same-net vias and track
|
||||
ends are also valid start/goal anchors.
|
||||
"""
|
||||
|
||||
from __future__ import annotations
|
||||
|
||||
import argparse
|
||||
import heapq
|
||||
import math
|
||||
import shutil
|
||||
import time
|
||||
from dataclasses import dataclass
|
||||
from pathlib import Path
|
||||
|
||||
import pcbnew
|
||||
|
||||
import route_local_power as rlp
|
||||
|
||||
|
||||
# A 0.20-mm grid lands on both halves of the Ti375's 0.8-mm dogbone lattice
|
||||
# while keeping the Python obstacle search tractable. Endpoint stubs retain
|
||||
# their exact coordinates, so off-grid package pads are not displaced.
|
||||
STEP = 0.20
|
||||
VIA_DIAMETER = 0.45
|
||||
VIA_DRILL = 0.225
|
||||
|
||||
CLASS_RULES = {
|
||||
"Default": (0.12, 0.10),
|
||||
"BGA_ESCAPE": (0.10, 0.10),
|
||||
"CLOCK": (0.15, 0.15),
|
||||
# Only low-current local rails may be passed to this finisher. Main 5-V
|
||||
# and converter paths need deterministic wide copper instead.
|
||||
"POWER": (0.25, 0.10),
|
||||
}
|
||||
|
||||
|
||||
def mm(value: int) -> float:
|
||||
return round(pcbnew.ToMM(value), 4)
|
||||
|
||||
|
||||
def MM(value: float) -> int:
|
||||
return pcbnew.FromMM(value)
|
||||
|
||||
|
||||
@dataclass(frozen=True)
|
||||
class Anchor:
|
||||
point: tuple[float, float]
|
||||
layers: tuple[int, ...]
|
||||
label: str
|
||||
|
||||
|
||||
class FineMaze:
|
||||
def __init__(self, board: pcbnew.BOARD) -> None:
|
||||
self.board = board
|
||||
self.layers = tuple(
|
||||
layer for layer in board.GetEnabledLayers().CuStack()
|
||||
if board.GetLayerType(layer) == pcbnew.LT_SIGNAL
|
||||
)
|
||||
self.layer_rank = {layer: index for index, layer in enumerate(self.layers)}
|
||||
self.obstacles = rlp.Obstacles(board)
|
||||
|
||||
def track_clear(self, net: str, a: tuple[float, float], b: tuple[float, float],
|
||||
layer: int, width: float, clearance: float) -> bool:
|
||||
return self.obstacles.track_clear(
|
||||
net, a, b, width, layer, clearance_floor=clearance
|
||||
)
|
||||
|
||||
def via_clear(self, net: str, p: tuple[float, float], clearance: float) -> bool:
|
||||
return self.obstacles.via_clear(net, p, clearance_floor=clearance)
|
||||
|
||||
@staticmethod
|
||||
def _collapse(points: list[tuple[float, float, int]]) -> list[tuple[float, float, int]]:
|
||||
if len(points) < 3:
|
||||
return points
|
||||
out = [points[0]]
|
||||
for index in range(1, len(points) - 1):
|
||||
a = out[-1]
|
||||
b = points[index]
|
||||
c = points[index + 1]
|
||||
if a[2] == b[2] == c[2]:
|
||||
cross = (b[0] - a[0]) * (c[1] - b[1]) - (b[1] - a[1]) * (c[0] - b[0])
|
||||
if abs(cross) < 1e-8:
|
||||
continue
|
||||
out.append(b)
|
||||
out.append(points[-1])
|
||||
return out
|
||||
|
||||
def search(self, net: str, start: Anchor, goal: Anchor, width: float,
|
||||
clearance: float, margin: float, deadline_s: float = 90.0,
|
||||
node_cap: int = 700_000) -> list[tuple[float, float, int]] | None:
|
||||
sx, sy = start.point
|
||||
gx, gy = goal.point
|
||||
x0 = min(sx, gx) - margin
|
||||
y0 = min(sy, gy) - margin
|
||||
x1 = max(sx, gx) + margin
|
||||
y1 = max(sy, gy) + margin
|
||||
|
||||
def snap(value: float) -> int:
|
||||
return round(value / STEP)
|
||||
|
||||
ix0, iy0 = snap(x0), snap(y0)
|
||||
ix1, iy1 = snap(x1), snap(y1)
|
||||
|
||||
def point(ix: int, iy: int) -> tuple[float, float]:
|
||||
return round(ix * STEP, 4), round(iy * STEP, 4)
|
||||
|
||||
def heuristic(ix: int, iy: int) -> float:
|
||||
px, py = point(ix, iy)
|
||||
return math.hypot(px - gx, py - gy)
|
||||
|
||||
start_layers = tuple(layer for layer in start.layers if layer in self.layer_rank)
|
||||
goal_layers = frozenset(layer for layer in goal.layers if layer in self.layer_rank)
|
||||
if not start_layers or not goal_layers:
|
||||
return None
|
||||
|
||||
queue: list[tuple[float, float, tuple[int, int, int]]] = []
|
||||
cost: dict[tuple[int, int, int], float] = {}
|
||||
parent: dict[tuple[int, int, int], tuple[int, int, int] | None] = {}
|
||||
|
||||
# Seed several nearby grid points. The exact pad/via/track endpoint to
|
||||
# grid stub is checked just like every other segment; no unchecked snap
|
||||
# segment can leak into the output.
|
||||
base_x, base_y = snap(sx), snap(sy)
|
||||
for layer in start_layers:
|
||||
for dx in (-1, 0, 1):
|
||||
for dy in (-1, 0, 1):
|
||||
ix, iy = base_x + dx, base_y + dy
|
||||
if not (ix0 <= ix <= ix1 and iy0 <= iy <= iy1):
|
||||
continue
|
||||
p = point(ix, iy)
|
||||
if p != start.point and not self.track_clear(
|
||||
net, start.point, p, layer, width, clearance):
|
||||
continue
|
||||
state = (ix, iy, layer)
|
||||
initial = math.hypot(p[0] - sx, p[1] - sy)
|
||||
if initial < cost.get(state, math.inf):
|
||||
cost[state] = initial
|
||||
parent[state] = None
|
||||
heapq.heappush(queue, (initial + heuristic(ix, iy), initial, state))
|
||||
|
||||
if not queue:
|
||||
return None
|
||||
|
||||
stop = time.monotonic() + deadline_s
|
||||
hit: tuple[int, int, int] | None = None
|
||||
visited = 0
|
||||
directions = ((-1, -1), (-1, 0), (-1, 1), (0, -1),
|
||||
(0, 1), (1, -1), (1, 0), (1, 1))
|
||||
|
||||
while queue and visited < node_cap and time.monotonic() < stop:
|
||||
_score, current_cost, state = heapq.heappop(queue)
|
||||
if current_cost > cost.get(state, math.inf) + 1e-9:
|
||||
continue
|
||||
visited += 1
|
||||
ix, iy, layer = state
|
||||
here = point(ix, iy)
|
||||
|
||||
if layer in goal_layers and math.hypot(here[0] - gx, here[1] - gy) <= 0.30:
|
||||
if here == goal.point or self.track_clear(
|
||||
net, here, goal.point, layer, width, clearance):
|
||||
hit = state
|
||||
break
|
||||
|
||||
for dx, dy in directions:
|
||||
nx, ny = ix + dx, iy + dy
|
||||
if not (ix0 <= nx <= ix1 and iy0 <= ny <= iy1):
|
||||
continue
|
||||
nxt_point = point(nx, ny)
|
||||
if not self.track_clear(net, here, nxt_point, layer, width, clearance):
|
||||
continue
|
||||
nxt = (nx, ny, layer)
|
||||
move = STEP * (math.sqrt(2.0) if dx and dy else 1.0)
|
||||
# Prefer inner signal layers slightly, but do not ban F/B.
|
||||
outer_penalty = 0.015 if layer in (pcbnew.F_Cu, pcbnew.B_Cu) else 0.0
|
||||
new_cost = current_cost + move + outer_penalty
|
||||
if new_cost + 1e-9 < cost.get(nxt, math.inf):
|
||||
cost[nxt] = new_cost
|
||||
parent[nxt] = state
|
||||
heapq.heappush(queue, (new_cost + heuristic(nx, ny), new_cost, nxt))
|
||||
|
||||
if self.via_clear(net, here, clearance):
|
||||
for next_layer in self.layers:
|
||||
if next_layer == layer:
|
||||
continue
|
||||
nxt = (ix, iy, next_layer)
|
||||
new_cost = current_cost + 2.0
|
||||
if new_cost + 1e-9 < cost.get(nxt, math.inf):
|
||||
cost[nxt] = new_cost
|
||||
parent[nxt] = state
|
||||
heapq.heappush(queue, (new_cost + heuristic(ix, iy), new_cost, nxt))
|
||||
|
||||
if hit is None:
|
||||
return None
|
||||
|
||||
states = []
|
||||
cursor: tuple[int, int, int] | None = hit
|
||||
while cursor is not None:
|
||||
states.append(cursor)
|
||||
cursor = parent[cursor]
|
||||
states.reverse()
|
||||
result = [(sx, sy, states[0][2])]
|
||||
result.extend((*point(ix, iy), layer) for ix, iy, layer in states)
|
||||
result.append((gx, gy, states[-1][2]))
|
||||
return self._collapse(result)
|
||||
|
||||
def _same_net_via_at(self, net: str, p: tuple[float, float]) -> bool:
|
||||
for item in self.board.GetTracks():
|
||||
if not isinstance(item, pcbnew.PCB_VIA) or item.GetNetname() != net:
|
||||
continue
|
||||
q = item.GetPosition()
|
||||
if math.hypot(mm(q.x) - p[0], mm(q.y) - p[1]) < 0.02:
|
||||
return True
|
||||
return False
|
||||
|
||||
def add_track(self, net: str, a: tuple[float, float], b: tuple[float, float],
|
||||
layer: int, width: float) -> None:
|
||||
if math.hypot(a[0] - b[0], a[1] - b[1]) < 1e-6:
|
||||
return
|
||||
track = pcbnew.PCB_TRACK(self.board)
|
||||
track.SetStart(pcbnew.VECTOR2I_MM(*a))
|
||||
track.SetEnd(pcbnew.VECTOR2I_MM(*b))
|
||||
track.SetWidth(MM(width))
|
||||
track.SetLayer(layer)
|
||||
track.SetNet(self.board.FindNet(net))
|
||||
track.SetLocked(True)
|
||||
self.board.Add(track)
|
||||
track.thisown = False
|
||||
self.obstacles.add_track(net, a, b, width, layer)
|
||||
|
||||
def add_via(self, net: str, p: tuple[float, float]) -> None:
|
||||
if self._same_net_via_at(net, p):
|
||||
return
|
||||
via = pcbnew.PCB_VIA(self.board)
|
||||
via.SetPosition(pcbnew.VECTOR2I_MM(*p))
|
||||
via.SetWidth(MM(VIA_DIAMETER))
|
||||
via.SetDrill(MM(VIA_DRILL))
|
||||
via.SetLayerPair(pcbnew.F_Cu, pcbnew.B_Cu)
|
||||
via.SetNet(self.board.FindNet(net))
|
||||
via.SetLocked(True)
|
||||
self.board.Add(via)
|
||||
via.thisown = False
|
||||
self.obstacles.add_via(net, p, VIA_DIAMETER / 2, VIA_DRILL / 2)
|
||||
|
||||
def commit(self, net: str, path: list[tuple[float, float, int]], width: float) -> None:
|
||||
for a, b in zip(path, path[1:]):
|
||||
if a[2] == b[2]:
|
||||
self.add_track(net, a[:2], b[:2], a[2], width)
|
||||
else:
|
||||
if math.hypot(a[0] - b[0], a[1] - b[1]) > 0.02:
|
||||
raise RuntimeError(f"Non-vertical layer change in {net}: {a} -> {b}")
|
||||
self.add_via(net, a[:2])
|
||||
|
||||
|
||||
def item_anchor(item, routing_layers: tuple[int, ...], label: str) -> list[Anchor]:
|
||||
if isinstance(item, pcbnew.PAD):
|
||||
p = item.GetPosition()
|
||||
layers = tuple(layer for layer in item.GetLayerSet().Seq() if layer in routing_layers)
|
||||
return [Anchor((mm(p.x), mm(p.y)), layers, label)] if layers else []
|
||||
if isinstance(item, pcbnew.PCB_VIA):
|
||||
p = item.GetPosition()
|
||||
return [Anchor((mm(p.x), mm(p.y)), routing_layers, label)]
|
||||
if isinstance(item, pcbnew.PCB_TRACK):
|
||||
layer = item.GetLayer()
|
||||
if layer not in routing_layers:
|
||||
return []
|
||||
a, b = item.GetStart(), item.GetEnd()
|
||||
return [Anchor((mm(a.x), mm(a.y)), (layer,), label + ":start"),
|
||||
Anchor((mm(b.x), mm(b.y)), (layer,), label + ":end")]
|
||||
return []
|
||||
|
||||
|
||||
def copper_groups(board: pcbnew.BOARD, net: str,
|
||||
routing_layers: tuple[int, ...]) -> list[tuple[list[pcbnew.PAD], list[Anchor]]]:
|
||||
connectivity = board.GetConnectivity()
|
||||
pads = [pad for fp in board.GetFootprints() for pad in fp.Pads()
|
||||
if pad.GetNetname() == net]
|
||||
seen: set[str] = set()
|
||||
groups = []
|
||||
for pad in pads:
|
||||
uid = pad.m_Uuid.AsString()
|
||||
if uid in seen:
|
||||
continue
|
||||
connected = list(connectivity.GetConnectedItems(pad, 0))
|
||||
if all(item.m_Uuid.AsString() != uid for item in connected):
|
||||
connected.append(pad)
|
||||
group_pads = [item for item in connected if isinstance(item, pcbnew.PAD)]
|
||||
if not group_pads:
|
||||
group_pads = [pad]
|
||||
seen.update(item.m_Uuid.AsString() for item in group_pads)
|
||||
anchors: list[Anchor] = []
|
||||
anchor_seen = set()
|
||||
for index, item in enumerate(connected):
|
||||
for anchor in item_anchor(item, routing_layers, f"{item.GetClass()}#{index}"):
|
||||
key = (anchor.point, anchor.layers)
|
||||
if key not in anchor_seen:
|
||||
anchors.append(anchor)
|
||||
anchor_seen.add(key)
|
||||
if not anchors:
|
||||
anchors.extend(item_anchor(pad, routing_layers, "pad"))
|
||||
groups.append((group_pads, anchors))
|
||||
return groups
|
||||
|
||||
|
||||
def class_rule(board: pcbnew.BOARD, net: str) -> tuple[float, float, str]:
|
||||
for fp in board.GetFootprints():
|
||||
for pad in fp.Pads():
|
||||
if pad.GetNetname() == net:
|
||||
name = pad.GetNetClassName()
|
||||
width, clearance = CLASS_RULES.get(name, CLASS_RULES["Default"])
|
||||
return width, clearance, name
|
||||
raise RuntimeError(f"Net {net} has no pads")
|
||||
|
||||
|
||||
def finish_net(maze: FineMaze, net: str) -> int:
|
||||
board = maze.board
|
||||
joined = 0
|
||||
while True:
|
||||
board.BuildConnectivity()
|
||||
groups = copper_groups(board, net, maze.layers)
|
||||
if len(groups) < 2:
|
||||
return joined
|
||||
groups.sort(key=lambda group: len(group[0]), reverse=True)
|
||||
main = groups[0]
|
||||
branch = min(groups[1:], key=lambda group: len(group[0]))
|
||||
width, clearance, class_name = class_rule(board, net)
|
||||
|
||||
pairs = []
|
||||
for source in branch[1]:
|
||||
for target in main[1]:
|
||||
distance = math.hypot(source.point[0] - target.point[0],
|
||||
source.point[1] - target.point[1])
|
||||
pairs.append((distance, source, target))
|
||||
pairs.sort(key=lambda entry: entry[0])
|
||||
routed = False
|
||||
for distance, source, target in pairs[:10]:
|
||||
for margin in (5.0, 12.0):
|
||||
path = maze.search(net, source, target, width, clearance, margin,
|
||||
deadline_s=20.0, node_cap=240_000)
|
||||
if path is None:
|
||||
continue
|
||||
maze.commit(net, path, width)
|
||||
board.BuildConnectivity()
|
||||
print(f"{net}: joined {source.label} -> {target.label}; "
|
||||
f"class={class_name} width={width:.3f} mm span={distance:.1f} mm")
|
||||
joined += 1
|
||||
routed = True
|
||||
break
|
||||
if routed:
|
||||
break
|
||||
if not routed:
|
||||
print(f"{net}: FAILED ({len(groups)} copper groups, {len(pairs)} anchor pairs)")
|
||||
return joined
|
||||
|
||||
|
||||
def main() -> None:
|
||||
parser = argparse.ArgumentParser()
|
||||
parser.add_argument("board", type=Path)
|
||||
parser.add_argument("--output", type=Path)
|
||||
parser.add_argument("--nets", required=True,
|
||||
help="Comma- or semicolon-separated residual net names")
|
||||
args = parser.parse_args()
|
||||
output = args.output or args.board
|
||||
nets = [name.strip() for name in args.nets.replace(";", ",").split(",")
|
||||
if name.strip()]
|
||||
|
||||
board = pcbnew.LoadBoard(str(args.board))
|
||||
if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
|
||||
raise RuntimeError("Zone refill failed before residual routing")
|
||||
board.BuildConnectivity()
|
||||
maze = FineMaze(board)
|
||||
|
||||
for net in nets:
|
||||
if board.FindNet(net) is None:
|
||||
raise RuntimeError(f"Unknown net: {net}")
|
||||
finish_net(maze, net)
|
||||
|
||||
if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
|
||||
raise RuntimeError("Zone refill failed after residual routing")
|
||||
board.BuildConnectivity()
|
||||
pcbnew.SaveBoard(str(output), board)
|
||||
if output != args.board:
|
||||
for suffix in (".kicad_pro", ".kicad_dru"):
|
||||
source = args.board.with_suffix(suffix)
|
||||
if source.exists():
|
||||
shutil.copyfile(source, output.with_suffix(suffix))
|
||||
print(f"Unconnected endpoints: {board.GetConnectivity().GetUnconnectedCount(True)}")
|
||||
print(f"Saved {output}")
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
+82
-70
@@ -1,5 +1,5 @@
|
||||
#!/usr/bin/env python3
|
||||
"""Create the placed eight-layer KiCad PCB from the audited design database.
|
||||
"""Create the placed ten-layer KiCad PCB from the audited design database.
|
||||
|
||||
The script is deterministic so placement, net assignments, stackup, and rules
|
||||
can be regenerated and independently audited. Routing uses the staged
|
||||
@@ -62,8 +62,15 @@ MAJOR = {
|
||||
|
||||
# USB-C and debug block.
|
||||
"J1": (23.1, 48, 270), "U5": (30.5, 44.5, 0), "U6": (30.5, 51.5, 0),
|
||||
"U2": (43, 55, 0), "U25": (35, 62, 0), "U3": (51, 63, 0),
|
||||
"U29": (60, 54.5, 0), "U30": (67, 58.5, 0), "U31": (62, 63.5, 0),
|
||||
"U2": (43, 55, 0), "U25": (35, 62, 0), "U3": (51, 65, 0),
|
||||
# The three FTDI-to-FPGA level buffers pulled west toward the FT4232H so
|
||||
# BDBUS/CDBUS source nets reach them without threading the whole cluster.
|
||||
"U29": (52.5, 54, 0), "U30": (60, 58, 0), "U31": (55.5, 62.5, 0),
|
||||
|
||||
# Dedicated USB-C power input, stacked in the gap between mounting hole H1
|
||||
# and the J1 debug block on the same west edge. U35 sits at the same
|
||||
# relative offset from J7 that U5 sits from J1.
|
||||
"J7": (23.1, 35, 270), "U35": (30.5, 31.5, 0),
|
||||
|
||||
# Mechanically quiet IMU region.
|
||||
"U22": (51, 84, 0),
|
||||
@@ -135,8 +142,11 @@ SPECIAL = {
|
||||
# MAX2771 output damping sits at the receiver; FPGA-driven 3-wire control
|
||||
# damping sits at the BGA source. R55 holds SHDN low at the receiver.
|
||||
"R45": (151.0, 44.5, 0),
|
||||
"R46": (154.6, 50.2, 90), "R47": (155.8, 50.2, 90),
|
||||
"R48": (157.0, 50.2, 90), "R49": (158.2, 50.2, 90),
|
||||
# Widened from 1.2 mm to 2.0 mm pitch and dropped 1.3 mm south of the
|
||||
# MAX2771 so each debug tap (MAX_I0_DEV etc.) has its own escape lane out
|
||||
# from under U21.
|
||||
"R46": (153.6, 51.5, 90), "R47": (155.6, 51.5, 90),
|
||||
"R48": (157.6, 51.5, 90), "R49": (159.6, 51.5, 90),
|
||||
"R50": (160.5, 47.5, 90),
|
||||
"R51": (121.5, 65.5, 0), "R52": (121.5, 66.7, 0),
|
||||
"R53": (121.5, 67.9, 0), "R54": (121.5, 69.1, 0),
|
||||
@@ -167,7 +177,7 @@ SPECIAL = {
|
||||
# connector-like test-point bank along the board edge.
|
||||
SPECIAL.update({
|
||||
"TP1": (37.5, 94.0, 0), "TP2": (45.5, 104.0, 0),
|
||||
"TP3": (166.5, 54.0, 0), "TP4": (29.0, 39.0, 0),
|
||||
"TP3": (166.5, 54.0, 0), "TP4": (30.5, 36.5, 0),
|
||||
"TP5": (22.0, 89.0, 0), "TP6": (49.5, 98.5, 0),
|
||||
"TP7": (66.5, 90.0, 0), "TP8": (105.0, 98.0, 0),
|
||||
"TP9": (118.0, 102.0, 0), "TP10": (133.0, 102.0, 0),
|
||||
@@ -326,22 +336,32 @@ def configure_rules(board: pcbnew.BOARD) -> None:
|
||||
|
||||
|
||||
def add_stackup(board: pcbnew.BOARD) -> None:
|
||||
board.SetCopperLayerCount(8)
|
||||
board.SetLayerName(pcbnew.In1_Cu, "L2_GND")
|
||||
board.SetLayerName(pcbnew.In2_Cu, "L3_SIG")
|
||||
board.SetLayerName(pcbnew.In3_Cu, "L4_PWR")
|
||||
# L5 is a routing layer, not a rail. Declaring it signal is what puts
|
||||
# it into the Specctra export as routable: a layer left as "power" is
|
||||
# offered to the router as "not used for routing", which is exactly the
|
||||
# congestion this stackup exists to avoid.
|
||||
board.SetLayerName(pcbnew.In4_Cu, "L5_SIG")
|
||||
board.SetLayerName(pcbnew.In5_Cu, "L6_PWR")
|
||||
board.SetLayerName(pcbnew.In6_Cu, "L7_GND")
|
||||
board.SetLayerType(pcbnew.In1_Cu, pcbnew.LT_POWER)
|
||||
board.SetLayerType(pcbnew.In3_Cu, pcbnew.LT_POWER)
|
||||
board.SetLayerType(pcbnew.In4_Cu, pcbnew.LT_SIGNAL)
|
||||
board.SetLayerType(pcbnew.In5_Cu, pcbnew.LT_POWER)
|
||||
board.SetLayerType(pcbnew.In6_Cu, pcbnew.LT_POWER)
|
||||
# Ten-layer 1.6 mm build. The Ti375 north-east escape carries ~54 signals
|
||||
# (bank 2E PMOD3/4 + the HVIO banks' PMOD1/2, the MAX2771 interface, both
|
||||
# JTAG chains, QSPI, IMU) out of a ~10 mm span; five routing layers gave
|
||||
# ~60 escape slots for 54 nets and the last handful never fit. Six routing
|
||||
# layers (F, L3, L5, L7, L9, B) restore the margin. L6 is the single power
|
||||
# plane - every rail lives there as an island - so it is the only layer the
|
||||
# escape cannot use, and it is not needed there. L2/L4/L8 are solid GND;
|
||||
# the outer F->L2 and L9->B prepreg is unchanged 3313 (0.0994 mm), so the
|
||||
# F.Cu 50-ohm CPWG and 90-ohm USB geometries carry over untouched.
|
||||
board.SetCopperLayerCount(10)
|
||||
names = {
|
||||
pcbnew.In1_Cu: "L2_GND", pcbnew.In2_Cu: "L3_SIG",
|
||||
pcbnew.In3_Cu: "L4_PWR", pcbnew.In4_Cu: "L5_SIG",
|
||||
pcbnew.In5_Cu: "L6_SIG", pcbnew.In6_Cu: "L7_GND",
|
||||
pcbnew.In7_Cu: "L8_PWR", pcbnew.In8_Cu: "L9_SIG",
|
||||
}
|
||||
for layer, name in names.items():
|
||||
board.SetLayerName(layer, name)
|
||||
# L2/L7 solid GND; L4 the core + front-end power plane; L8 the two big FPGA
|
||||
# I/O rails (VCC3V3 background, VCC1V8 carved). Both power planes sit
|
||||
# between GND and a routing layer, and neither is a layer the BGA escape
|
||||
# needs, so all six routing layers (F, L3, L5, L6, L9, B) stay clean.
|
||||
for layer in (pcbnew.In1_Cu, pcbnew.In3_Cu, pcbnew.In6_Cu, pcbnew.In7_Cu):
|
||||
board.SetLayerType(layer, pcbnew.LT_POWER)
|
||||
for layer in (pcbnew.In2_Cu, pcbnew.In4_Cu, pcbnew.In5_Cu, pcbnew.In8_Cu):
|
||||
board.SetLayerType(layer, pcbnew.LT_SIGNAL)
|
||||
|
||||
|
||||
def place_components(board: pcbnew.BOARD) -> dict[str, pcbnew.FOOTPRINT]:
|
||||
@@ -510,26 +530,21 @@ def add_zone(board: pcbnew.BOARD, net_name: str, layer: int,
|
||||
|
||||
|
||||
def add_power_planes(board: pcbnew.BOARD) -> None:
|
||||
"""Ground on L2/L7, and the supply rails split across L4 and L6.
|
||||
"""Ten-layer power: solid GND on L2/L7 and B.Cu, the core + front-end rails
|
||||
on the L4 plane, and the two big FPGA I/O rails on the L8 plane.
|
||||
|
||||
No rail owns a whole layer. L4 carries the core, the 5-V input rail, the
|
||||
always-on auxiliary rail and the four 3.0-V front-end rails; L6 carries the
|
||||
two large FPGA I/O rails. That leaves L3, L5 and B.Cu free for routing,
|
||||
which is where the Ti375's fanout has to go.
|
||||
Both power planes sit between a GND plane and a routing layer. Neither is
|
||||
a layer the Ti375 escape needs, so all six routing layers (F, L3, L5, L6,
|
||||
L9, B) stay clean and the I/O-rail pads stitch straight into L8 instead of
|
||||
needing a via to a buried background.
|
||||
"""
|
||||
# Continuous reference planes immediately below the two outer signal
|
||||
# layers. A 0.50-mm inset exceeds JLCPCB's copper-to-edge requirement.
|
||||
# These are the return path for every routed layer, so they use the tight
|
||||
# anti-pad clearance and stay continuous through the Ti375 via field. L2
|
||||
# in particular is the reference under the whole GPS front end and is never
|
||||
# split between "RF ground" and "digital ground".
|
||||
full = (X0 + 0.50, Y0 + 0.50, X1 - 0.50, Y1 - 0.50)
|
||||
for layer in (pcbnew.In1_Cu, pcbnew.In6_Cu):
|
||||
add_zone(board, "GND", layer, (X0 + 0.50, Y0 + 0.50, X1 - 0.50, Y1 - 0.50),
|
||||
clearance=PLANE_CLEARANCE)
|
||||
add_zone(board, "GND", layer, full, clearance=PLANE_CLEARANCE)
|
||||
add_zone(board, "GND", pcbnew.B_Cu, full, priority=0, clearance=0.20)
|
||||
|
||||
# L4: everything except the two big I/O rails. Islands follow the
|
||||
# functional floorplan; no high-speed route uses L4 and no signal crosses a
|
||||
# split on either adjacent routing layer without a nearby return via.
|
||||
# L4 (In3_Cu): core plus the 5-V input, the always-on auxiliary rail and
|
||||
# the four 3.0-V front-end rails. Islands follow the functional floorplan.
|
||||
l4 = (
|
||||
("VCC3V3_AUX", (20.50, 36.00, 74.00, 72.00)),
|
||||
("VCC3V3_AUX", (53.00, 88.00, 70.00, 105.00)),
|
||||
@@ -537,8 +552,6 @@ def add_power_planes(board: pcbnew.BOARD) -> None:
|
||||
("VCC3V3_AUX", (133.00, 74.50, 152.00, 82.00)),
|
||||
("SYS5", (20.50, 85.50, 52.50, 109.50)),
|
||||
("SYS5", (89.50, 103.60, 145.00, 109.50)),
|
||||
# A corridor up the east edge carries 5 V to the antenna-bias block
|
||||
# instead of leaving those three pads stranded 55 mm from the rail.
|
||||
("SYS5", (140.00, 103.00, 174.50, 109.50)),
|
||||
("SYS5", (144.00, 86.50, 174.50, 104.00)),
|
||||
("SYS5", (157.00, 72.00, 174.50, 87.00)),
|
||||
@@ -546,9 +559,6 @@ def add_power_planes(board: pcbnew.BOARD) -> None:
|
||||
("VCC3V0_CLK", (126.00, 48.50, 156.00, 67.00)),
|
||||
("VCC3V0_RF", (140.00, 58.50, 150.50, 65.50)),
|
||||
("VCC3V0_DIG", (134.00, 62.50, 147.00, 74.00)),
|
||||
# Core balls are interspersed with GND/auxiliary balls, so a complete
|
||||
# local patch (with automatic anti-pads) replaces any voltage split
|
||||
# crossing the BGA field.
|
||||
("VCC0V95", (94.50, 56.00, 121.00, 103.00)),
|
||||
("VCC3V0_RF", (146.00, 39.80, 174.50, 50.50)),
|
||||
("VCC3V0_DIG", (149.00, 35.20, 161.00, 39.60)),
|
||||
@@ -556,27 +566,22 @@ def add_power_planes(board: pcbnew.BOARD) -> None:
|
||||
("VCC3V3_ANT", (162.00, 53.50, 174.50, 63.20)),
|
||||
)
|
||||
for priority, (net_name, bounds) in enumerate(l4, 1):
|
||||
# Only the core island sits under the BGA and needs the tight anti-pad.
|
||||
add_zone(board, net_name, pcbnew.In3_Cu, bounds, priority,
|
||||
clearance=PLANE_CLEARANCE if net_name == "VCC0V95" else 0.20)
|
||||
|
||||
# L6: the two FPGA I/O rails. VCC3V3 is the background because its loads
|
||||
# are spread over the whole west and the RF corner; VCC1V8 is carved out
|
||||
# where its own loads sit - under the BGA, along the 1.8-V PMOD headers,
|
||||
# over the configuration flash and at its converter output. The carve-outs
|
||||
# overlap each other so the rail stays one connected pour.
|
||||
l6 = (
|
||||
# Overlapping zones need distinct priorities even when they carry the
|
||||
# same net, so the carve-outs are numbered rather than sharing one.
|
||||
("VCC3V3", (X0 + 0.50, Y0 + 0.50, X1 - 0.50, Y1 - 0.50), 1),
|
||||
# L8 (In7_Cu): the two big FPGA I/O rails. VCC3V3 is the board-wide
|
||||
# background; VCC1V8 is carved out under the BGA config banks, along the
|
||||
# 1.8-V PMOD headers, over the configuration flash and at its converter.
|
||||
l8 = (
|
||||
("VCC3V3", full, 1),
|
||||
("VCC1V8", (99.00, 39.50, 122.00, 92.00), 10),
|
||||
("VCC1V8", (115.00, 20.50, 174.50, 40.50), 11),
|
||||
("VCC1V8", (94.00, 45.00, 106.00, 56.00), 12),
|
||||
("VCC1V8", (108.50, 91.50, 127.00, 106.00), 13),
|
||||
("VCC3V3", (128.00, 91.50, 141.00, 106.00), 20),
|
||||
)
|
||||
for net_name, bounds, priority in l6:
|
||||
add_zone(board, net_name, pcbnew.In5_Cu, bounds, priority,
|
||||
for net_name, bounds, priority in l8:
|
||||
add_zone(board, net_name, pcbnew.In7_Cu, bounds, priority,
|
||||
clearance=PLANE_CLEARANCE)
|
||||
|
||||
|
||||
@@ -587,7 +592,7 @@ def add_power_planes(board: pcbnew.BOARD) -> None:
|
||||
# F.Cu along the exact paths that finalize_routing.py later builds, since the
|
||||
# critical nets themselves are not part of the Specctra export.
|
||||
CRITICAL_KEEPOUTS_BELOW = (
|
||||
("TEMP_RF_NO_DIGITAL_BELOW", (152.00, 36.00, 174.50, 49.50)),
|
||||
("TEMP_RF_NO_DIGITAL_BELOW", (152.00, 36.00, 174.50, 43.70)),
|
||||
("TEMP_USB_NO_CROSSING_BELOW", (26.00, 46.00, 39.60, 56.60)),
|
||||
)
|
||||
CRITICAL_KEEPOUTS_CORRIDOR = (
|
||||
@@ -611,12 +616,15 @@ def add_temporary_critical_keepouts(board: pcbnew.BOARD) -> None:
|
||||
finalize_routing.py removes every TEMP_ area before installing the audited
|
||||
copper, so nothing here reaches the manufactured board.
|
||||
"""
|
||||
# Every copper layer under F.Cu except the solid GND planes (L2/L7): the
|
||||
# routing layers L3/L5/L6/L9/B and the L4/L8 power planes.
|
||||
inner = (pcbnew.In2_Cu, pcbnew.In3_Cu, pcbnew.In4_Cu, pcbnew.In5_Cu,
|
||||
pcbnew.In7_Cu, pcbnew.In8_Cu, pcbnew.B_Cu)
|
||||
below = pcbnew.LSET()
|
||||
for layer in (pcbnew.In2_Cu, pcbnew.In4_Cu, pcbnew.In5_Cu, pcbnew.B_Cu):
|
||||
for layer in inner:
|
||||
below.AddLayer(layer)
|
||||
corridor = pcbnew.LSET()
|
||||
for layer in (pcbnew.F_Cu, pcbnew.In2_Cu, pcbnew.In4_Cu,
|
||||
pcbnew.In5_Cu, pcbnew.B_Cu):
|
||||
for layer in (pcbnew.F_Cu,) + inner:
|
||||
corridor.AddLayer(layer)
|
||||
|
||||
for layers, group in ((below, CRITICAL_KEEPOUTS_BELOW),
|
||||
@@ -641,8 +649,8 @@ def add_temporary_critical_keepouts(board: pcbnew.BOARD) -> None:
|
||||
|
||||
def add_documentation_graphics(board: pcbnew.BOARD) -> None:
|
||||
add_text(board, "Ti375 GNSS / SCH16T", 105, 33.0, 1.1)
|
||||
add_text(board, "REV A1 JLC08161H-3313 8L", 105, 35.2, 0.8)
|
||||
add_text(board, "USB-C 5V", 31, 35.5, 0.9)
|
||||
add_text(board, "REV A1 JLC10161H 10L", 105, 35.2, 0.8)
|
||||
add_text(board, "USB-C PWR", 37, 30, 0.8)
|
||||
add_text(board, "EXT_5V", 28, 108.0, 0.9)
|
||||
add_text(board, "GPS L1/L1C ACTIVE", 162, 34, 0.9)
|
||||
add_text(board, "BIAS J5: 3V3-OFF-5V", 163, 72, 0.8)
|
||||
@@ -665,17 +673,21 @@ STACKUP = '''\t\t(stackup
|
||||
\t\t\t(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||
\t\t\t(layer "dielectric 1" (type "prepreg") (thickness 0.0994) (material "JLC 3313") (epsilon_r 4.1) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L2_GND" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 2" (type "core") (thickness 0.1) (material "JLC FR-4 core") (epsilon_r 4.36) (loss_tangent 0.02))
|
||||
\t\t\t(layer "dielectric 2" (type "core") (thickness 0.19) (material "JLC FR-4 core") (epsilon_r 4.4) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L3_SIG" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 3" (type "prepreg") (thickness 0.3568) (material "JLC 3x2116") (epsilon_r 4.16) (loss_tangent 0.02))
|
||||
\t\t\t(layer "dielectric 3" (type "prepreg") (thickness 0.15) (material "JLC 2116") (epsilon_r 4.16) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L4_PWR" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 4" (type "core") (thickness 0.3) (material "JLC FR-4 core") (epsilon_r 4.41) (loss_tangent 0.02))
|
||||
\t\t\t(layer "dielectric 4" (type "core") (thickness 0.19) (material "JLC FR-4 core") (epsilon_r 4.4) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L5_SIG" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 5" (type "prepreg") (thickness 0.3568) (material "JLC 3x2116") (epsilon_r 4.16) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L6_PWR" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 6" (type "core") (thickness 0.1) (material "JLC FR-4 core") (epsilon_r 4.36) (loss_tangent 0.02))
|
||||
\t\t\t(layer "dielectric 5" (type "prepreg") (thickness 0.15) (material "JLC 2116") (epsilon_r 4.16) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L6_SIG" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 6" (type "core") (thickness 0.19) (material "JLC FR-4 core") (epsilon_r 4.4) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L7_GND" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 7" (type "prepreg") (thickness 0.0994) (material "JLC 3313") (epsilon_r 4.1) (loss_tangent 0.02))
|
||||
\t\t\t(layer "dielectric 7" (type "prepreg") (thickness 0.15) (material "JLC 2116") (epsilon_r 4.16) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L8_PWR" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 8" (type "core") (thickness 0.19) (material "JLC FR-4 core") (epsilon_r 4.4) (loss_tangent 0.02))
|
||||
\t\t\t(layer "L9_SIG" (type "copper") (thickness 0.0152))
|
||||
\t\t\t(layer "dielectric 9" (type "prepreg") (thickness 0.0994) (material "JLC 3313") (epsilon_r 4.1) (loss_tangent 0.02))
|
||||
\t\t\t(layer "B.Cu" (type "copper") (thickness 0.035))
|
||||
\t\t\t(layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
|
||||
\t\t\t(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||
@@ -708,8 +720,8 @@ def main() -> None:
|
||||
title.SetTitle("Ti375 C529 GPS L1/L1C + SCH16T acquisition board")
|
||||
title.SetRevision("A0")
|
||||
title.SetCompany("JLCPCB manufacturing design")
|
||||
title.SetComment(0, "USB-C 5 V primary; protected EXT_5V; no back-feed")
|
||||
title.SetComment(1, "JLC08161H-3313 exact eight-layer construction")
|
||||
title.SetComment(0, "J7 USB-C 5 V or EXT_5V, muxed, never both; J1 debug-only, no back-feed")
|
||||
title.SetComment(1, "JLC10161H exact ten-layer construction; F->L2 and L9->B keep 3313 for F.Cu impedance")
|
||||
if not pcbnew.ZONE_FILLER(board).Fill(board.Zones()):
|
||||
raise RuntimeError("Initial inner-plane fill failed")
|
||||
pcbnew.SaveBoard(str(BOARD_FILE), board)
|
||||
|
||||
+106
-26
@@ -79,14 +79,21 @@ SKIP_REFS = {"J2"}
|
||||
# Every ground land under the GPS front end is connected by that same RF ground
|
||||
# zone and its via fence. Ordinary dogbones here would only add long stubs
|
||||
# alongside the controlled-impedance line.
|
||||
# The F.Cu ground pour over the whole GPS front end.
|
||||
RF_GROUND_REGION = (152.0, 36.0, 174.5, 49.5)
|
||||
|
||||
# The band the RF line actually occupies, and the only part of the front end
|
||||
# that has to stay clear of digital copper on the layers below F.Cu. The
|
||||
# MAX2771's own digital pins sit south of it (pin rows at y = 44.5 .. 47.4)
|
||||
# and need those layers to escape the package at all.
|
||||
RF_NO_DIGITAL_REGION = (152.0, 36.0, 174.5, 43.7)
|
||||
# Nothing but ground and the MAX2771's own supplies may run under the GPS front
|
||||
# end on a layer other than F.Cu. This router is the one stage that runs after
|
||||
# finalize_routing.py has deleted the temporary keepout, so it has to carry the
|
||||
# restriction itself; without it the deterministic completion is free to drop a
|
||||
# charge-pump or control net onto L3 directly beneath the 50-ohm line.
|
||||
RF_REGION_LAYERS = (pcbnew.In2_Cu, pcbnew.In3_Cu, pcbnew.In4_Cu,
|
||||
pcbnew.In5_Cu, pcbnew.B_Cu)
|
||||
RF_REGION_LAYERS = (pcbnew.In2_Cu, pcbnew.In3_Cu, pcbnew.In4_Cu, pcbnew.In5_Cu,
|
||||
pcbnew.In7_Cu, pcbnew.In8_Cu, pcbnew.B_Cu)
|
||||
|
||||
|
||||
def rf_region_forbids(net: str, layer: int | None) -> bool:
|
||||
@@ -103,8 +110,8 @@ def rf_region_forbids(net: str, layer: int | None) -> bool:
|
||||
|
||||
|
||||
def in_rf_region(position: tuple[float, float], margin: float = 0.0) -> bool:
|
||||
return (RF_GROUND_REGION[0] - margin <= position[0] <= RF_GROUND_REGION[2] + margin and
|
||||
RF_GROUND_REGION[1] - margin <= position[1] <= RF_GROUND_REGION[3] + margin)
|
||||
return (RF_NO_DIGITAL_REGION[0] - margin <= position[0] <= RF_NO_DIGITAL_REGION[2] + margin and
|
||||
RF_NO_DIGITAL_REGION[1] - margin <= position[1] <= RF_NO_DIGITAL_REGION[3] + margin)
|
||||
MAX_PLANE_REACH = 7.0
|
||||
# A dogbone via never sits further than this from the pad it escapes.
|
||||
ESCAPE_VIA_REACH = 0.8
|
||||
@@ -148,6 +155,64 @@ def segment_distance(p: tuple[float, float], a: tuple[float, float],
|
||||
return math.hypot(p[0] - (a[0] + t * dx), p[1] - (a[1] + t * dy))
|
||||
|
||||
|
||||
def _seg_aabb_distance(start: tuple[float, float], end: tuple[float, float],
|
||||
x0: float, y0: float, x1: float, y1: float) -> float:
|
||||
"""Exact distance from a segment to an axis-aligned box (0 if they touch)."""
|
||||
for probe in (start, end):
|
||||
if x0 <= probe[0] <= x1 and y0 <= probe[1] <= y1:
|
||||
return 0.0
|
||||
corners = ((x0, y0), (x1, y0), (x1, y1), (x0, y1))
|
||||
return min(segments_distance(start, end, corners[i], corners[(i + 1) % 4])
|
||||
for i in range(4))
|
||||
|
||||
|
||||
def pad_point_distance(shape: tuple[float, float, float, float, float],
|
||||
probe: tuple[float, float]) -> float:
|
||||
"""Distance from a point to a pad, as an oriented rounded rectangle.
|
||||
|
||||
`shape` is (cx, cy, hx, hy, r): centre, half extents and corner radius.
|
||||
A circle is hx = hy = 0 with r = radius; a plain rectangle is r = 0. This
|
||||
replaces the old bounding-box test, which measured a diagonal neighbour
|
||||
from the box edge instead of the land itself and so rejected every legal
|
||||
0.8-mm BGA dogbone site.
|
||||
"""
|
||||
cx, cy, hx, hy, r = shape
|
||||
dx = max(abs(probe[0] - cx) - hx, 0.0)
|
||||
dy = max(abs(probe[1] - cy) - hy, 0.0)
|
||||
return max(math.hypot(dx, dy) - r, 0.0)
|
||||
|
||||
|
||||
def pad_segment_distance(shape: tuple[float, float, float, float, float],
|
||||
start: tuple[float, float],
|
||||
end: tuple[float, float]) -> float:
|
||||
"""Distance from a segment to a pad modelled as a rounded rectangle."""
|
||||
cx, cy, hx, hy, r = shape
|
||||
return max(_seg_aabb_distance(start, end, cx - hx, cy - hy,
|
||||
cx + hx, cy + hy) - r, 0.0)
|
||||
|
||||
|
||||
def pad_shape(pad: pcbnew.PAD) -> tuple[float, float, float, float, float]:
|
||||
"""Analytic (cx, cy, hx, hy, r) for a pad, exact for every shape on this
|
||||
board (circle, oval, rectangle, rounded rectangle) at 0 or 90 degrees."""
|
||||
position = pad.GetPosition()
|
||||
cx, cy = to_mm(position.x), to_mm(position.y)
|
||||
size_x, size_y = to_mm(pad.GetSizeX()) / 2, to_mm(pad.GetSizeY()) / 2
|
||||
if round(pad.GetOrientationDegrees()) % 180 == 90:
|
||||
size_x, size_y = size_y, size_x
|
||||
shape = pad.GetShape()
|
||||
if shape == pcbnew.PAD_SHAPE_CIRCLE:
|
||||
return (cx, cy, 0.0, 0.0, min(size_x, size_y))
|
||||
if shape == pcbnew.PAD_SHAPE_OVAL:
|
||||
radius = min(size_x, size_y)
|
||||
return (cx, cy, size_x - radius, size_y - radius, radius)
|
||||
if shape == pcbnew.PAD_SHAPE_ROUNDRECT:
|
||||
radius = min(to_mm(pad.GetRoundRectCornerRadius()), size_x, size_y)
|
||||
return (cx, cy, size_x - radius, size_y - radius, radius)
|
||||
# rectangle, trapezoid, custom and anything else: the bounding box, which
|
||||
# is what the model used everywhere before.
|
||||
return (cx, cy, size_x, size_y, 0.0)
|
||||
|
||||
|
||||
def segments_distance(a0: tuple[float, float], a1: tuple[float, float],
|
||||
b0: tuple[float, float], b1: tuple[float, float]) -> float:
|
||||
"""Minimum distance between two segments, including the crossing case."""
|
||||
@@ -167,7 +232,16 @@ class Obstacles:
|
||||
|
||||
CELL = 5.0
|
||||
|
||||
def __init__(self, board: pcbnew.BOARD) -> None:
|
||||
def __init__(self, board: pcbnew.BOARD,
|
||||
escape_refs: frozenset[str] | None = None,
|
||||
escape_clearance: float = 0.10) -> None:
|
||||
# Footprints whose pads carry a DRC rule that overrides the net-class
|
||||
# clearance -- on this board the "Ti375 0.8-mm BGA escape clearance"
|
||||
# rule in board.kicad_dru, which allows 0.10 mm whenever one of the two
|
||||
# objects belongs to U1. Opt-in: every existing caller keeps the plain
|
||||
# net-class behaviour.
|
||||
self.escape_refs = frozenset(escape_refs or ())
|
||||
self.escape_clearance = escape_clearance
|
||||
self.board = board
|
||||
self.cells: dict[tuple[int, int], list] = defaultdict(list)
|
||||
self.holes: list[tuple[tuple[float, float], float]] = []
|
||||
@@ -176,8 +250,9 @@ class Obstacles:
|
||||
box = pad.GetBoundingBox()
|
||||
bounds = (to_mm(box.GetX()), to_mm(box.GetY()),
|
||||
to_mm(box.GetRight()), to_mm(box.GetBottom()))
|
||||
self._insert(("pad", pad.GetNetname(), bounds,
|
||||
pad.GetLayerSet()), bounds)
|
||||
self._insert(("pad", pad.GetNetname(), pad_shape(pad),
|
||||
pad.GetLayerSet(),
|
||||
footprint.GetReference()), bounds)
|
||||
drill = max(to_mm(pad.GetDrillSizeX()), to_mm(pad.GetDrillSizeY()))
|
||||
if drill > 0:
|
||||
position = pad.GetPosition()
|
||||
@@ -294,21 +369,12 @@ class Obstacles:
|
||||
continue
|
||||
clearance = max(floor, STRICT_CLEARANCE.get(entry[1], 0.0))
|
||||
if entry[0] == "pad":
|
||||
_, _, box, layers = entry
|
||||
_, _, shape, layers, ref = entry
|
||||
if not layers.Contains(layer):
|
||||
continue
|
||||
margin = half + clearance
|
||||
corners = ((box[0], box[1]), (box[2], box[1]),
|
||||
(box[2], box[3]), (box[0], box[3]))
|
||||
inflated = (box[0] - margin, box[1] - margin,
|
||||
box[2] + margin, box[3] + margin)
|
||||
for probe in (start, end):
|
||||
if (inflated[0] <= probe[0] <= inflated[2] and
|
||||
inflated[1] <= probe[1] <= inflated[3]):
|
||||
return False
|
||||
for index in range(4):
|
||||
if segments_distance(start, end, corners[index],
|
||||
corners[(index + 1) % 4]) < margin:
|
||||
if ref in self.escape_refs:
|
||||
clearance = self.escape_clearance
|
||||
if pad_segment_distance(shape, start, end) < half + clearance:
|
||||
return False
|
||||
elif entry[0] == "via":
|
||||
_, _, position, radius = entry
|
||||
@@ -343,10 +409,10 @@ class Obstacles:
|
||||
continue
|
||||
clearance = max(floor, STRICT_CLEARANCE.get(entry[1], 0.0))
|
||||
if entry[0] == "pad":
|
||||
_, _, box, _layers = entry
|
||||
margin = radius + clearance
|
||||
if (box[0] - margin <= position[0] <= box[2] + margin and
|
||||
box[1] - margin <= position[1] <= box[3] + margin):
|
||||
_, _, shape, _layers, ref = entry
|
||||
if ref in self.escape_refs:
|
||||
clearance = self.escape_clearance
|
||||
if pad_point_distance(shape, position) < radius + clearance:
|
||||
return False
|
||||
elif entry[0] == "via":
|
||||
_, _, other, other_radius = entry
|
||||
@@ -806,9 +872,23 @@ def complete(board: pcbnew.BOARD, verbose: bool = True,
|
||||
remaining[net] = left
|
||||
|
||||
if signals:
|
||||
router.widths = signal_nets(board, signal_classes)
|
||||
# The Specctra import normally completes hundreds of signal nets. A
|
||||
# full BuildConnectivity inside route_net() for every already-finished
|
||||
# net made this post-pass spend several minutes proving the same fact
|
||||
# twice. Build once, retain only nets that are genuinely split, and
|
||||
# run the unchanged router over that exact residual set.
|
||||
board.BuildConnectivity()
|
||||
all_widths = signal_nets(board, signal_classes)
|
||||
router.widths = {
|
||||
name: width for name, width in all_widths.items()
|
||||
if len(groups_for_net(board, name)) > 1
|
||||
}
|
||||
router.clearance = SIGNAL_CLEARANCE
|
||||
router.clearances = signal_clearances(board, signal_classes)
|
||||
router.clearances = {
|
||||
name: clearance
|
||||
for name, clearance in signal_clearances(board, signal_classes).items()
|
||||
if name in router.widths
|
||||
}
|
||||
closed = 0
|
||||
for detour in (False, True):
|
||||
for net in sorted(router.widths):
|
||||
|
||||
Reference in New Issue
Block a user