Restack to four signal layers and route the board

The Ti375 fanout could not be resolved with three routing layers, so L5
stops being a dedicated 1.8-V plane and becomes a signal layer.  No rail
owns a whole layer any more: the supplies are split into zone islands on
L4 and L6, L2 and L7 stay solid and completely unrouted, and F.Cu, L3, L5
and B.Cu are all available for signals.

Routing is staged rather than handed to the autorouter wholesale.  The
BGA escape, the buck high-current loops, plane stitching and the local
power completion all run first and are locked; Freerouting then sees only
the ordinary digital classes, with everything else present as fixed
copper.  finalize_routing.py installs the audited RF and USB geometry and
closes whatever the autorouter left.

Four bugs behind the routing failures, all of them the same shape - a
layer list written down instead of read from the board, which was correct
while L5 was a plane and silently wrong afterwards:

- export_routing_stage.py emitted via keepouts for three layers only, so
  every existing via was invisible to the router on L5.  It drove traces
  straight through them: 102 shorting_items in DRC.
- route_local_power.py never used L5 at all, and picked up escape vias on
  two layers instead of all four.
- add_rf_ground() judged fence positions against vias and pads but not
  tracks.  It runs after the session import, when that region already has
  routed copper, and dropped a ground via on top of a signal trace.

route_local_power.py also grew a via cloud on every rail: reaching a
plane counted as progress even when it merged nothing, so the same pad
collected a via per pass, 0.4 mm further out each time.  Progress is now
measured by the group count actually falling, and groups already sitting
on their plane are skipped.  That removed 404 redundant vias.

The MAX2771 PLL loop filter was spread across three corners of the
package, which forced the charge-pump node onto an inner layer under the
GPS front end.  All three parts now sit in the pocket at U21's north-west
corner and the net stays on F.Cu.  A permanent RF_NO_DIGITAL area plus a
scoped rule keeps that region free of non-power copper on L3/L5/L6/B.Cu,
and the local router enforces the same restriction, since it is the one
stage that runs after the temporary keepout is deleted.

Also enables the solder-mask bridge check that was switched off
board-wide; the board passes it with no violations.

Final board: DRC clean - no shorts, clearance, disallowed-item or
dangling-copper violations - with 26 unconnected endpoints left.  Routing
is spread 37% L3, 27% F.Cu, 26% L5, 10% B.Cu over 6548 mm and 971 vias.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

scripts/preroute_bga.py

@@ -22,6 +22,10 @@ def mm(value: float) -> int:
     return pcbnew.FromMM(value)
 
 
+def centre_mm(position: pcbnew.VECTOR2I) -> tuple[float, float]:
+    return pcbnew.ToMM(position.x), pcbnew.ToMM(position.y)
+
+
 def add_segment(board: pcbnew.BOARD, pad: pcbnew.PAD,
                 end: pcbnew.VECTOR2I, width_mm: float) -> None:
     track = pcbnew.PCB_TRACK(board)
@@ -46,10 +50,25 @@ def add_via(board: pcbnew.BOARD, pad: pcbnew.PAD,
     board.Add(via)
 
 
+def ball_grid(footprint: pcbnew.FOOTPRINT) -> tuple[dict, float, float, float, float]:
+    """Every ball position, connected or not, plus the array extent."""
+    positions = {}
+    for pad in footprint.Pads():
+        p = pad.GetPosition()
+        positions[(round(pcbnew.ToMM(p.x), 2), round(pcbnew.ToMM(p.y), 2))] = pad
+    xs = [x for x, _ in positions]
+    ys = [y for _, y in positions]
+    return positions, min(xs), min(ys), max(xs), max(ys)
+
+
 def main() -> None:
     parser = argparse.ArgumentParser()
     parser.add_argument("input", nargs="?", type=Path, default=DEFAULT_INPUT)
     parser.add_argument("output", nargs="?", type=Path, default=DEFAULT_OUTPUT)
+    parser.add_argument("--surface-rings", type=int, default=1,
+                        help="How many outer ball rings escape on F.Cu without "
+                             "a via. Each via removed here frees an inner-layer "
+                             "channel and one anti-pad per plane.")
     args = parser.parse_args()
 
     board = pcbnew.LoadBoard(str(args.input))
@@ -58,12 +77,37 @@ def main() -> None:
         raise RuntimeError("U1 Ti375 footprint is missing")
     centre = fpga.GetPosition()
     occupied: set[tuple[int, int]] = set()
-    counts = {"power": 0, "signal": 0}
+    counts = {"power": 0, "signal": 0, "surface": 0}
+    _grid, gx0, gy0, gx1, gy1 = ball_grid(fpga)
+    pitch = 0.8
 
     for pad in fpga.Pads():
         if not pad.GetNetname():
             continue
         position = pad.GetPosition()
+        x, y = pcbnew.ToMM(position.x), pcbnew.ToMM(position.y)
+        ring = min(round((x - gx0) / pitch), round((gx1 - x) / pitch),
+                   round((y - gy0) / pitch), round((gy1 - y) / pitch))
+        is_power = pad.GetNetname() in POWER_NETS
+        # Signal balls on the outer rings leave straight out on F.Cu.  They
+        # need no via at all, and the interstitial site they would have taken
+        # stays open as a channel for the balls further in.  Power and ground
+        # balls always drop, because their whole purpose is to reach a plane.
+        if not is_power and ring < args.surface_rings:
+            dx = 0.0 if abs(x - centre_mm(centre)[0]) < 0.4 else (
+                1.0 if x > centre_mm(centre)[0] else -1.0)
+            dy = 0.0 if abs(y - centre_mm(centre)[1]) < 0.4 else (
+                1.0 if y > centre_mm(centre)[1] else -1.0)
+            if abs(x - centre_mm(centre)[0]) > abs(y - centre_mm(centre)[1]):
+                dy = 0.0
+            else:
+                dx = 0.0
+            reach = 1.6
+            end = pcbnew.VECTOR2I(position.x + mm(dx * reach),
+                                  position.y + mm(dy * reach))
+            add_segment(board, pad, end, 0.10)
+            counts["surface"] += 1
+            continue
         # Move each ball toward its package quadrant.  Centre-row/column balls
         # use the positive direction, leaving a full 0.8-mm via grid without
         # duplicated interstitial locations.
@@ -74,7 +118,6 @@ def main() -> None:
         if key in occupied:
             raise RuntimeError(f"Duplicate dogbone via at {key} for U1.{pad.GetNumber()}")
         occupied.add(key)
-        is_power = pad.GetNetname() in POWER_NETS
         add_segment(board, pad, via_position, 0.15 if is_power else 0.10)
         add_via(board, pad, via_position)
         counts["power" if is_power else "signal"] += 1
@@ -86,7 +129,8 @@ def main() -> None:
         source = args.input.with_suffix(suffix)
         if source.exists():
             shutil.copyfile(source, args.output.with_suffix(suffix))
-    print(f"Installed {counts['power']} power/GND and {counts['signal']} signal dogbones")
+    print(f"Installed {counts['power']} power/GND and {counts['signal']} signal "
+          f"dogbones, {counts['surface']} via-less surface escapes")
     print(f"Saved {args.output}")