pcb/docs/ti375_pinout.csv

1	signal	ball	official_pin_name	die_bank	package_bank	vccio	io_standard	direction	clock_capability	special_function	subsystem	connector	connector_pin	note
2	IMU_DRY_SYNC	A11	GPIOR_93_PLLIN1	TR1	TR1	3.3 V	3.3 V LVCMOS	bidirectional	no	PLL_INPUT	sch16t	on-board		Murata multiplexed Data Ready output / SYNC input
3	PMOD1_3	A13	GPIOR_94	TR1	TR1	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr1	JPMOD1	3	PMOD 1 pin 3
4	PMOD4_2	A14	GPIOT_N_55	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	2	PMOD 4 pin 2; HSIO pair 55 N
5	PMOD3_7	A16	GPIOT_P_53	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	7	PMOD 3 pin 7; HSIO pair 53 P
6	PMOD3_8	A17	GPIOT_N_53	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	8	PMOD 3 pin 8; HSIO pair 53 N
7	PMOD4_7	A18	GPIOT_P_57	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	7	PMOD 4 pin 7; HSIO pair 57 P
8	PMOD4_8	A19	GPIOT_N_57	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	8	PMOD 4 pin 8; HSIO pair 57 N
9	QSPI_CS_N	A7	GPIOB_N_38_SSL_N	4B	4A_4B	1.8 V	1.8 V LVCMOS	output	no	DIFFERENTIAL_MEMBER	configuration	on-board		SPI-active SSL_N
10	IMU_SCK	A8	GPIOR_170	BR3	BR3_BR4	3.3 V	3.3 V LVCMOS	output	no		sch16t	on-board		SafeSPI mode-0 clock
11	IMU_MOSI	A9	GPIOR_171	BR3	BR3_BR4	3.3 V	3.3 V LVCMOS	output	no		sch16t	on-board		SafeSPI controller-to-sensor data
12	IMU_CS	B10	GPIOR_169	BR3	BR3_BR4	3.3 V	3.3 V LVCMOS	output	no		sch16t	on-board		SafeSPI active-low chip select
13	MAX_CLKOUT	B11	GPIOR_143_CLK9	BR0	BR0	3.0 V	3.0 V LVCMOS	input	yes	CLOCK_CAPABLE	max2771	on-board		Source-synchronous ADC capture clock on dedicated clock-capable input
14	PMOD4_1	B14	GPIOT_P_55	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	1	PMOD 4 pin 1; HSIO pair 55 P
15	PMOD3_4	B17	GPIOT_N_52	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	4	PMOD 3 pin 4; HSIO pair 52 N
16	PMOD3_10	B19	GPIOT_N_54	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	10	PMOD 3 pin 10; HSIO pair 54 N
17	PMOD3_2	B20	GPIOT_N_51	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	2	PMOD 3 pin 2; HSIO pair 51 N
18	QSPI_IO3	B7	GPIOB_P_38_CDI3	4B	4A_4B	1.8 V	1.8 V LVCMOS	bidirectional	no	CORE_DATA_INPUT;DIFFERENTIAL_MEMBER	configuration	on-board		SPI-active CDI3
19	IMU_MISO	B9	GPIOR_168	BR3	BR3_BR4	3.3 V	3.3 V LVCMOS	input	no		sch16t	on-board		SafeSPI sensor-to-controller data
20	IMU_EXTRESN	C10	GPIOR_167	BR3	BR3_BR4	3.3 V	3.3 V LVCMOS	output	no		sch16t	on-board		External active-low reset
21	PMOD1_7	C12	GPIOR_99	TR1	TR1	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr1	JPMOD1	7	PMOD 1 pin 7
22	PMOD1_8	C13	GPIOR_98	TR1	TR1	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr1	JPMOD1	8	PMOD 1 pin 8
23	PMOD1_9	C14	GPIOR_97	TR1	TR1	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr1	JPMOD1	9	PMOD 1 pin 9
24	PMOD3_3	C17	GPIOT_P_52	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	3	PMOD 3 pin 3; HSIO pair 52 P
25	PMOD3_9	C19	GPIOT_P_54	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	9	PMOD 3 pin 9; HSIO pair 54 P
26	PMOD3_1	C20	GPIOT_P_51	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD3	1	PMOD 3 pin 1; HSIO pair 51 P
27	PMOD1_4	C9	GPIOR_166	BR3	BR3_BR4	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_3v3	JPMOD1	4	PMOD 1 pin 4; plain HVIO GPIO
28	MAX_I0	D10	GPIOR_144	BR0	BR0	3.0 V	3.0 V LVCMOS	input	no		max2771	on-board		ADC I bit 0
29	MAX_I1	D11	GPIOR_142_CLK8	BR0	BR0	3.0 V	3.0 V LVCMOS	input	yes	CLOCK_CAPABLE	max2771	on-board		ADC I bit 1; clock-capable pad retained in same BR0 bank
30	PMOD1_10	D12	GPIOR_100	TR1	TR1	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr1	JPMOD1	10	PMOD 1 pin 10
31	PMOD2_2	D13	GPIOR_102	TR2	TR2	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr2	JPMOD2	2	PMOD 2 pin 2
32	PMOD4_9	D16	GPIOT_P_58	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	9	PMOD 4 pin 9; HSIO pair 58 P
33	PMOD4_10	D17	GPIOT_N_58	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	10	PMOD 4 pin 10; HSIO pair 58 N
34	MAX_Q0	E10	GPIOR_145_PLLIN1	BR0	BR0	3.0 V	3.0 V LVCMOS	input	no	PLL_INPUT	max2771	on-board		ADC Q bit 0; PLL-capable pad in same BR0 bank
35	MAX_Q1	E11	GPIOR_140_PLLIN1	BR0	BR0	3.0 V	3.0 V LVCMOS	input	no	PLL_INPUT	max2771	on-board		ADC Q bit 1; PLL-capable pad in same BR0 bank
36	PMOD2_3	E13	GPIOR_103	TR2	TR2	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr2	JPMOD2	3	PMOD 2 pin 3
37	PMOD2_4	E14	GPIOR_104	TR2	TR2	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr2	JPMOD2	4	PMOD 2 pin 4
38	PMOD2_9	E15	GPIOR_107	TR2	TR2	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr2	JPMOD2	9	PMOD 2 pin 9
39	PMOD2_7	E16	GPIOR_105	TR2	TR2	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr2	JPMOD2	7	PMOD 2 pin 7
40	MAX_LD	F11	GPIOR_141	BR0	BR0	3.0 V	3.0 V LVCMOS	input	no		max2771	on-board		PLL lock status
41	RISCV_TCK	F12	GPIOR_101_PLLIN1	TR2	TR2	3.3 V	3.3 V LVCMOS	input	no	PLL_INPUT	secondary_jtag	on-board		Fabric RISC-V JTAG clock moved off the plain-GPIO PMOD allocation
42	PMOD2_8	F13	GPIOR_106	TR2	TR2	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr2	JPMOD2	8	PMOD 2 pin 8
43	PMOD2_10	F14	GPIOR_108	TR2	TR2	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_tr2	JPMOD2	10	PMOD 2 pin 10
44	MAX_SCLK	F16	GPIOR_90	TR0	TR0	3.0 V	3.0 V LVCMOS	output	no		max2771	on-board		Three-wire serial clock
45	MAX_CSN	F17	GPIOR_91	TR0	TR0	3.0 V	3.0 V LVCMOS	output	no		max2771	on-board		Three-wire active-low chip select
46	FPGA_CDONE	F8	CDONE	4A	4A_4B	1.8 V	1.8 V LVCMOS	output	no		configuration	on-board		Configuration status test point
47	FPGA_CRESET_N	F9	CRESET_N	4A	4A_4B	1.8 V	1.8 V LVCMOS	input	no	DIFFERENTIAL_MEMBER	configuration	on-board		Open-drain fan-in of all-rail-valid, FTDI, and filtered external/manual reset requests
48	HARD_TCK	G10	TCK	BR4	BR3_BR4	3.3 V	3.3 V LVCMOS	input	no		hard_jtag	on-board		Dedicated hard TAP TCK; FT4232H interface 1 BDBUS0 through power-domain isolation
49	HARD_TMS	G12	TMS	BR4	BR3_BR4	3.3 V	3.3 V LVCMOS	input	no		hard_jtag	on-board		Dedicated hard TAP TMS; FT4232H interface 1 BDBUS3 through power-domain isolation
50	HARD_TDO	G13	TDO	BR4	BR3_BR4	3.3 V	3.3 V LVCMOS	output	no		hard_jtag	on-board		Dedicated hard TAP TDO; FT4232H interface 1 BDBUS2 through power-domain isolation
51	MAX_SDATA	G16	GPIOR_89	TR0	TR0	3.0 V	3.0 V LVCMOS	bidirectional	no		max2771	on-board		Single bidirectional three-wire serial data; not split MOSI/MISO
52	MAX_SHDN	G17	GPIOR_92	TR0	TR0	3.0 V	3.0 V LVCMOS	output	no		max2771	on-board		MAX2771 hardware shutdown control
53	QSPI_IO2	G5	GPIOB_N_39_CDI2	4B	4A_4B	1.8 V	1.8 V LVCMOS	bidirectional	no	CORE_DATA_INPUT;DIFFERENTIAL_MEMBER	configuration	on-board		SPI-active CDI2
54	QSPI_SCLK	G6	GPIOB_P_39_CCK_PLLIN0	4B	4A_4B	1.8 V	1.8 V LVCMOS	output	no	PLL_INPUT;DIFFERENTIAL_MEMBER	configuration	on-board		SPI-active CCK; official CCK_PLLIN0 pin
55	HARD_TDI	G9	TDI	BR4	BR3_BR4	3.3 V	3.3 V LVCMOS	input	no		hard_jtag	on-board		Dedicated hard TAP TDI; FT4232H interface 1 BDBUS1 through power-domain isolation
56	PMOD4_4	H18	GPIOT_N_56	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	4	PMOD 4 pin 4; HSIO pair 56 N
57	QSPI_IO0	H4	GPIOB_N_40_CDI0	4B	4A_4B	1.8 V	1.8 V LVCMOS	bidirectional	no	CORE_DATA_INPUT;DIFFERENTIAL_MEMBER	configuration	on-board		SPI-active CDI0
58	QSPI_IO1	H5	GPIOB_P_40_CDI1_EXTFB	4B	4A_4B	1.8 V	1.8 V LVCMOS	bidirectional	no	PLL_EXTFB;CORE_DATA_INPUT;DIFFERENTIAL_MEMBER	configuration	on-board		SPI-active CDI1
59	PMOD4_3	J18	GPIOT_P_56	2E	2E	1.8 V	1.8 V LVCMOS	bidirectional	no	DIFFERENTIAL_MEMBER	pmod_2e	JPMOD4	3	PMOD 4 pin 3; HSIO pair 56 P
60	FPGA_TEST_N	J2	GPIOB_N_19_TEST_N_CLK6_N	4C	4C	1.8 V	1.8 V LVCMOS	input	yes	CLOCK_CAPABLE;DIFFERENTIAL_MEMBER	configuration	on-board		Mandatory external weak pull-up disables test mode during configuration
61	FPGA_CSI	J5	GPIOB_N_43_CSI_CLK10_N	4B	4A_4B	1.8 V	1.8 V LVCMOS	input	yes	CLOCK_CAPABLE;DIFFERENTIAL_MEMBER	configuration	on-board		Mandatory external weak pull-up selects this FPGA throughout configuration
62	UART0_RX	P17	GPIOL_84	TL5	TL1_TL5	3.3 V	3.3 V LVCMOS	input	no		ft4232	on-board		FT4232H channel C TXD to FPGA RX
63	RISCV_TMS	P18	GPIOL_80_CLK29	TL5	TL1_TL5	3.3 V	3.3 V LVCMOS	input	yes	CLOCK_CAPABLE	secondary_jtag	on-board		Clock-capable fabric pin; official development-kit assignment
64	UART0_TX	R17	GPIOL_85_PLLIN1	TL5	TL1_TL5	3.3 V	3.3 V LVCMOS	output	no	PLL_INPUT	ft4232	on-board		FPGA TX to FT4232H channel C RXD
65	UART1_RX	R18	GPIOL_87_PLLIN1	TL5	TL1_TL5	3.3 V	3.3 V LVCMOS	input	no	PLL_INPUT	ft4232	on-board		FT4232H channel D TXD to FPGA RX
66	RISCV_TDO	T18	GPIOL_83	TL5	TL1_TL5	3.3 V	3.3 V LVCMOS	output	no		secondary_jtag	on-board		Official development-kit hardened RISC-V JTAG assignment
67	UART1_TX	T19	GPIOL_86	TL5	TL1_TL5	3.3 V	3.3 V LVCMOS	output	no		ft4232	on-board		FPGA TX to FT4232H channel D RXD
68	CLK_40M_FPGA	U17	GPIOL_79_CLK28	TL5	TL1_TL5	3.3 V	3.3 V LVCMOS	input	yes	CLOCK_CAPABLE	clock	on-board		40 MHz oscillator branch on clock-capable pin
69	FTDI_DBG_GPIO	U19	GPIOL_52_PLLIN1	TL1	TL1_TL5	3.3 V	3.3 V LVCMOS	bidirectional	no	PLL_INPUT	ft4232	on-board		Channel D debug GPIO/test point; PLL-capable
70	PMOD1_1	U6	GPIOL_24	BL2	BL2_BL3	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_3v3	JPMOD1	1	PMOD 1 pin 1; plain HVIO GPIO
71	RISCV_TDI	V19	GPIOL_46	TL1	TL1_TL5	3.3 V	3.3 V LVCMOS	input	no		secondary_jtag	on-board		Official development-kit hardened RISC-V JTAG assignment
72	PMOD2_1	V20	GPIOL_45	TL1	TL1_TL5	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_3v3	JPMOD2	1	PMOD 2 pin 1; plain HVIO GPIO
73	PMOD1_2	V4	GPIOL_23	BL2	BL2_BL3	3.3 V	3.3 V LVCMOS	bidirectional	no		pmod_3v3	JPMOD1	2	PMOD 1 pin 2; plain HVIO GPIO