onur
791ca5c9fa
The routed deliverable has always been eight layers (JLC08161H-3313), but generate_pcb.py still emitted ten and hardware/board.kicad_pcb was itself still a ten-layer board. Source and generator agreed with each other and disagreed with what is actually being fabricated, so running the documented regeneration flow would have silently replaced the eight-layer design with a conflicting ten-layer one and destroyed the routing. generate_pcb.py now builds the real stack: SetCopperLayerCount(8), no L8_PWR / L9_SIG, and the STACKUP string taken verbatim from board_routed.kicad_pcb - the two are now byte-identical. Silkscreen reads JLC08161H-3313 8L instead of JLC10161H 10L, and the title block follows. The zone layout follows the same correction. With only one dedicated power plane there is no third plane for the two big FPGA I/O rails, so they are carried as islands on the routing layers that have room: VCC1V8 on L6 and VCC3V3 on B.Cu, replacing the ten-layer arrangement of a VCC3V3 background on L8 and a board-wide GND pour on B.Cu. The regenerated board now reproduces the routed board's 26 copper zones exactly (the 27th, the F.Cu RF ground pour, is added later by finalize_routing). Also drops the In7_Cu/In8_Cu remnants from finalize_routing's RF_NO_DIGITAL layer set and route_local_power's RF_REGION_LAYERS - those layers do not exist on this board, so they were dead bits in a layer mask - and corrects the JLC10161H reference in board.kicad_dru. The placement check now reports 21 isolated_copper warnings rather than 17. That is expected and explained in README.md: on an unrouted board the I/O-rail islands on L6 and B.Cu have nothing joining them yet. The routed board still reports zero. Verified: regenerated board is 8 layers with a stackup identical to the routed board, 312 footprints (311 + R108), TEMP keepouts at their corrected extents. design_data assertions pass, ERC 0/0, routed board still 0 DRC violations, 0 unconnected, every net one copper group, parity unchanged at 402. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
Çıktılar
Bu klasör build/routing çalışma alanıdır. Repository'de yalnızca güncel ve anlamlı teslim çıktıları tutulur:
bom.csv: ayrıntılı mühendislik BOM'u.jlcpcb_bom.csv: montaj servisi için sadeleştirilmiş BOM.erc_final_reset.rpt: güncel şema ERC raporu; 0 ihlal.drc_final_placement.rpt: unrouted placement DRC raporu.drc_power_local.rpt: sinyal routing'inden önceki güç katı DRC raporu.drc_final_routed.rpt: routed kart DRC raporu.board_final_reset_top.png: güncel üst görünüm.
Routing çalışma dosyaları:
signal_stage.dsn/signal_stage.ses: autorouter'a verilen ve ondan alınan sinyal katı. Sadeceboard_power_local.kicad_pcbile birlikte anlamlıdır.signal_stage_preview.kicad_pcb: DSN'e giren bakırın KiCad'de incelenebilir hâli.freerouting_signal.log: pass başına unrouted/violation sayısı.
Eski .dsn, .ses, preview PCB ve ara DRC raporları yeni netlist için
authoritative değildir. .dsn her zaman onu üreten karta bağlıdır: placement,
güç bakırı veya keepout değiştiğinde export ve routing baştan yapılmalıdır,
yoksa import edilen sonuç mevcut bakırla çakışır.
Final routed raporda sıfır açık bağlantı, sıfır clearance/short ve sıfır
schematic-parity hatası hedeflenir. Unrouted aşamadaki unconnected_items,
via_dangling ve isolated_copper kayıtları normaldir: sırasıyla henüz
çekilmemiş bağlantıları, henüz kullanılmayan BGA escape via'larını ve final
fill'de silinecek plane parçalarını gösterir.