onur
4fa38e35bd
The 0.164/0.200 CPWG geometry was fine; the calculation just stopped at the trace and never covered the connector launch, which is where the real discontinuity was. J2's centre land is 1.5 mm wide because that is what the connector's centre pin needs mechanically. Sitting on solid L2_GND only 0.0994 mm below, that land is a 10.7 ohm transmission line, not a 50 ohm one. The 1.84 mm of it over the plane is 6.7 degrees at L1 and reflects 12 dB (VSWR 1.67) - by far the worst discontinuity in the chain, and worse than everything the carefully built 0.164 mm line downstream avoids. RF_LAUNCH_RELIEF voids L2_GND and L3_SIG under the land, (172.35, 40.95) to (175.10, 43.05). The reference drops to L4_PWR - VCC3V0_RF, an AC ground - 0.587 mm below, which raises the launch to 37 ohm and 30 dB. L3 carried no pour and no copper there, so only L2 actually had to go; the area covers L3 as well so a later edit cannot fill the gap back in. It stops where the land ends and the 0.164 mm line begins, verified: L2 GND is absent across the whole land and present again at x = 172.0 and inboard. D1's ESD clamp sat at the end of a 1.34 mm spur, where its 0.3 pF presented -j228 ohm and cost 3.4 dB for nothing. D1 is rotated onto the run at (171.30, 42.416) so pad 1 overlaps the line directly and pad 2 lands in the RF ground pour; the spur is deleted. Return loss, worst term first: SMA launch land 12.0 -> 30.0 dB (10.7 -> 37.0 ohm) D1 ESD clamp 19.2 -> 22.6 dB (now just the part's own 0.3 pF) C85 DNP tuning stub 25.5 dB unchanged, intentional provision C84 DNP land in line 30.1 dB unchanged, negligible worst-case coherent 7.0 -> 14.4 dB The dominant term is now a component choice rather than a layout defect. Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group, parity unchanged at the 402 pre-existing warnings, RF still 10 segments all on F.Cu at exactly 0.164 mm. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
22 lines
751 B
Plaintext
22 lines
751 B
Plaintext
Board: hardware/board_routed.kicad_pcb
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Unconnected endpoints reported by connectivity: 0
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Tracks: 3067 Vias: 1020
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Track segments per layer:
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F.Cu 1747
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L6_SIG 482
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L5_SIG 390
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L3_SIG 387
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B.Cu 61
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Track width used per net class (mm: segments):
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BGA_ESCAPE 0.1: 423
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CLOCK 0.1: 17, 0.15: 145
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Default 0.1: 37, 0.12: 1375, 0.15: 5
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POWER 0.1: 79, 0.12: 4, 0.15: 193, 0.163: 18, 0.195: 1, 0.2: 4, 0.22: 12, 0.227: 3, 0.25: 248, 0.26: 6, 0.3: 327, 0.35: 1, 0.4: 103, 0.45: 2, 0.5: 2, 0.55: 10, 0.6: 4, 0.7: 2, 0.8: 5, 1.0: 1, 1.2: 4, 1.5: 2
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RF50_CPWG 0.164: 10
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USB90_DIFF 0.135: 24
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Nets still split into more than one copper group:
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none - every net is one connected group
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