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1ea2bc64ac
The power mux's status output had no pull-up, which broke the USB current budget interlock. TPS2121 ST is an open-drain output; the datasheet lists RST = 6-20 kOhm under Recommended Operating Conditions, alongside RILM, so it is an external part. ST is driven low only while IN2 (the J3 external 5 V header) is sourcing OUT, and is high impedance whenever IN1 (the J7 USB-C input) is sourcing. U10 gate 2 inverts MUX_ST into EXT_SELECTED, and MAIN_EN = USB_3A_OK OR EXT_SELECTED enables the 15 A core buck. With MUX_ST floating on USB-C power, a drift low asserts MAIN_EN no matter what the TUSB320 advertised, so the board would try to bring up the core rail on a 500 mA port. Every other open-drain net here already has its pull-up (R7/R8, R30, R33/R34, R98/R104/R105/R106); this one was missed. R108 (10 k, VCC3V3_AUX -> MUX_ST) is appended at the end of design_data.py rather than beside the mux: reference designators are assigned in call order, so inserting it mid-file would renumber every later resistor and invalidate the routed board. Placed at (53.0, 101.6), 2.4 mm from the U10 gate it holds up, on a site checked clear of existing copper, and routed with close_remaining.py. Also corrects POWER_TREE.md, which credited PR1 for giving the external input priority. PR1 = GND actually *disables* priority mode; CP2 (tied to VCC3V3_AUX) is what selects IN2. Since CP2 derives from the mux's own output the behaviour is two-phase - highest-voltage wins at cold start, IN2 unconditionally once the aux rail is up - so with both inputs connected there can be one seamless switchover at startup. Documented, with the numbers: both eFuses UV 3.98 V / OV 5.80 V, ILIM 2.69 A (USB-C) and 4.04 A (header), mux OV 5.69 V / ILIM 4.5 A. The two inputs are never summed: both eFuses block reverse current and the mux bonds exactly one input at a time. board_routed.kicad_sch/.kicad_sym are now gitignored byte copies of the tracked schematic; kicad-cli needs them beside the board for --schematic-parity, and deleting them in the previous commit had silently disabled that check. Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group, schematic parity unchanged at the 402 pre-existing warnings. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
Türetilmiş tasarım verileri
Bu klasördeki CSV/ISF dosyaları elle düzenlenecek ana tasarım kaynağı değildir;
scripts/design_data.py ve scripts/generate_design_tables.py üzerinden tekrar
üretilir.
Okunabilir tasarım dokümanları:
COMPONENT_SELECTION.md: ana IC seçimi, besleme ve kapasite sınırları.INTERFACES.md: RF, MAX2771, SafeSPI, QSPI, FTDI/USB ve test noktaları.FPGA_PINOUT.md: FPGA ball/bank/gerilim ve dört PMOD eşlemesi.POWER_TREE.md: giriş power-path, rail sıralaması, supervisor ve reset.
| Dosya | Açıklama |
|---|---|
ti375_c529_package.csv |
Efinity 2025.2 Ti375C529 paket veritabanından çıkarılmış 529 ball kaydı |
ti375_c529_package.meta.json |
Paket verisinin kaynak/sürüm metadatası |
ti375_pinout.csv |
Kartta kullanılan sinyal, ball, bank, VCCIO, I/O standardı ve konnektör eşlemesi |
unused_gpio_inventory.csv |
Kullanılan ve fiziksel olarak boş bırakılan fabric GPIO envanteri |
ti375_pin_constraints.isf |
HDL/Efinity tarafı için pin ve I/O standardı constraintleri |
max2771_registers.csv |
Kartın MAX2771 başlangıç register görüntüsü |
Yeniden üretmek için:
python3 scripts/generate_design_tables.py
Script aşağıdaki koşulları doğrular:
- Paket kaynağında tam 529 benzersiz ball bulunması.
- Dedicated TCK/TMS/TDI/TDO, CRESET_N, CDONE ve JTAG_VCCIO_SEL adları.
- Seçilen bankın istenen 3.3 V, 3.0 V veya 1.8 V I/O standardını desteklemesi.
- PMOD tahsislerinde konfigürasyon/PLL/clock özel fonksiyonlarının yanlışlıkla kullanılmaması.
- MAX2771 ve SCH16T için ayrılmış pinlerle PMOD çakışması olmaması.
Hard JTAG yalnızca kart üzerindeki FT4232H interface 1 üzerinden erişilir;
harici ARM/JTAG headerı yoktur. FPGA_CRESET_N, açık-drenç power/FTDI/harici
reset fan-in'i olarak belgelenmiştir.