onur
95609a6b6a
The board now routes end to end. Every net carrying two or more pads is a single connected copper group (216 nets, 1175 pads); kicad-cli reports 0 DRC violations and 0 unconnected items with zones refilled. Freerouting was never the blocker. The 14 remaining opens were three separate defects: 1. Obstacles in route_local_power.py modelled every pad as its axis-aligned bounding box. A 0.8-mm BGA dogbone site sits diagonally between four lands: true clearance 0.1407 mm, but the box test measured 0.4 mm from the box edge and rejected it, so no via could be placed anywhere in the Ti375 escape field. Replaced with an exact rounded-rectangle model, validated against KiCad's own SHAPE::Collide to 0.00 um over 14850 samples. Same 0 DRC and one fewer unconnected at the route_local_power stage. 2. CLOCK's 0.15-mm clearance cannot physically escape the BGA: two adjacent 0.45-mm dogbone vias on 0.8-mm pitch leave a 0.35-mm channel and a 0.10-mm trace needs 0.40 mm. HARD_TCK and MAX_SCLK could never leave the package. New rule "Ti375 escape field copper clearance" relaxes clearance to the 0.10 mm this field already uses, only where both objects are inside U1's courtyard. The clock trunk keeps 0.15 mm outside it. 3. RF_NO_DIGITAL was a rectangle reaching 7 mm past the RF line, covering the MAX2771's whole digital pin field and forcing every U21 output onto F.Cu alone. Narrowed to the corridor generate_pcb.py already reserves as TEMP_RF_LINE (y <= 43.7), clearing RF copper by 1.1 mm. The RF return path is guaranteed by the unrouted L2/L7 ground planes, not by this area. scripts/close_remaining.py replaces the ad-hoc residual scripts: a multi-layer maze over (x, y, layer) at 0.1 mm on all five routable layers, seeded from all copper of both groups, exact clearances, 0.10-mm necking inside the escape field, and reversible rip-up that rolls back entirely if a displaced net cannot be put back. ~150 s for the whole board. Also removes the regenerable intermediate boards, one-off session logs and the superseded residual scripts, and tracks board_routed.* as the deliverable. The 402 schematic-parity warnings are pre-existing and unchanged: 199 auto-named unconnected pins, 199 footprint library-nickname mismatches, and 4 mounting holes with no symbol. None affects connectivity or fabrication. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
85 lines
4.5 KiB
Plaintext
85 lines
4.5 KiB
Plaintext
(version 1)
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# The edge-launch SMA copper must reach the routed board edge by construction.
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(rule "J2 edge-launch lands"
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(condition "A.Reference == 'J2' || B.Reference == 'J2'")
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(constraint edge_clearance (min -0.01mm)))
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# The manufacturer USB-C locating holes are 0.194 mm from grounded shell
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# lands. This exception is internal to the qualified connector footprint.
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(rule "USB-C locating-hole clearance"
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(condition "A.Reference == 'J1' && B.Reference == 'J1'")
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(constraint hole_clearance (min 0.19mm)))
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# RZV0024A is an ultra-dense high-current package. Its adjusted corner lands
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# and thermal zones meet the selected JLCPCB 0.10-mm copper rule.
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(rule "TPS6287B RZV internal clearance"
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(condition "A.Reference == 'U13' && B.Reference == 'U13'")
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(constraint clearance (min 0.10mm)))
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# Inside the Ti375 escape field the 0.8-mm ball pitch fixes the geometry: a
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# 0.45-mm dogbone via between four lands leaves 0.1407 mm, and a 0.12-mm trace
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# threading between two lands leaves 0.14 mm only if it stays exactly centred.
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# This field therefore runs at the fabricator's 0.10-mm copper minimum, which
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# is what the Default class uses across the rest of the board anyway. The rule
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# only fires when one of the two objects belongs to U1, so it relaxes copper
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# against the balls and nothing else: two tracks crossing the field still owe
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# each other their own net classes' clearance, CLOCK's 0.15 mm included.
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(rule "Ti375 0.8-mm BGA escape clearance"
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(condition "A.Reference == 'U1' || B.Reference == 'U1'")
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(constraint clearance (min 0.10mm)))
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# JLC10161H L1/L2 geometry (F->L2 prepreg unchanged from the 8L build). Net-class widths are routing defaults only;
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# these rules make the controlled-impedance geometries actual DRC limits.
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(rule "GNSS 50-ohm CPWG geometry"
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(condition "A.NetClass == 'RF50_CPWG'")
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(constraint track_width (min 0.164mm) (opt 0.164mm) (max 0.164mm)))
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(rule "GNSS RF stays on top layer"
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(condition "A.NetClass == 'RF50_CPWG' && A.Type == 'Track' && A.Layer != 'F.Cu'")
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(constraint disallow track))
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(rule "USB2 90-ohm differential geometry"
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(condition "A.NetClass == 'USB90_DIFF'")
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(constraint track_width (min 0.135mm) (opt 0.135mm) (max 0.135mm)))
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# The TPD2EUSB30A clamp is a SOT-23 whose ground pad sits between its two
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# channel pads, so the pair has to open up for about 1.5 mm to pass it. The
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# 0.90-mm coupled limit still applies over the whole rest of the run.
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(rule "USB2 coupled gap"
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(condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair() && !A.intersectsArea('USB_ESD_BREAKOUT')")
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(constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.90mm)))
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# The 50-ohm line owns the band it runs in on every layer under F.Cu, so no
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# digital route can pass beneath or immediately beside it. Ground stitching
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# and the MAX2771's own supply drops still have to reach it, so the disallow is
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# scoped to the signal classes rather than made a plain keepout. The RF line
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# itself is on F.Cu, which the area does not cover, and the L2/L7 GND planes
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# stay solid because nothing routes on them at all -- the actual RF return path
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# is guaranteed by those planes, not by this area.
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#
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# The area covers y <= 43.7, which is the same corridor generate_pcb.py
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# reserves as TEMP_RF_LINE and clears the RF copper (y <= 42.6) by 1.1 mm. It
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# deliberately stops short of the MAX2771's digital pin rows at y = 44.5 ..
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# 47.4: those pins have to reach the FPGA, and with the area extended over them
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# every one of them was forced onto F.Cu alone, which does not fit.
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(rule "No digital copper under the GNSS front end"
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(condition "A.intersectsArea('RF_NO_DIGITAL') && A.NetClass != 'POWER'")
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(constraint disallow track via))
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(rule "Clock trunk width outside Ti375 escape"
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(condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')")
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(constraint track_width (min 0.15mm)))
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# A 0.8-mm ball pitch leaves a 0.35-mm channel between two adjacent 0.45-mm
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# dogbone vias. A 0.10-mm trace fits that channel at the escape field's
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# 0.10-mm copper minimum but not at CLOCK's 0.15 mm, so a clock ball could not
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# be escaped from the package at all. Inside the field -- and only where BOTH
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# objects are inside it -- copper therefore runs at the same 0.10 mm the rest
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# of this field already uses. The clock trunk keeps its 0.15 mm the moment it
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# leaves U1's courtyard, which is where coupling to neighbours actually costs
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# something.
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(rule "Ti375 escape field copper clearance"
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(condition "A.insideCourtyard('U1') && B.insideCourtyard('U1')")
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(constraint clearance (min 0.10mm)))
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