onur
4fa38e35bd
The 0.164/0.200 CPWG geometry was fine; the calculation just stopped at the trace and never covered the connector launch, which is where the real discontinuity was. J2's centre land is 1.5 mm wide because that is what the connector's centre pin needs mechanically. Sitting on solid L2_GND only 0.0994 mm below, that land is a 10.7 ohm transmission line, not a 50 ohm one. The 1.84 mm of it over the plane is 6.7 degrees at L1 and reflects 12 dB (VSWR 1.67) - by far the worst discontinuity in the chain, and worse than everything the carefully built 0.164 mm line downstream avoids. RF_LAUNCH_RELIEF voids L2_GND and L3_SIG under the land, (172.35, 40.95) to (175.10, 43.05). The reference drops to L4_PWR - VCC3V0_RF, an AC ground - 0.587 mm below, which raises the launch to 37 ohm and 30 dB. L3 carried no pour and no copper there, so only L2 actually had to go; the area covers L3 as well so a later edit cannot fill the gap back in. It stops where the land ends and the 0.164 mm line begins, verified: L2 GND is absent across the whole land and present again at x = 172.0 and inboard. D1's ESD clamp sat at the end of a 1.34 mm spur, where its 0.3 pF presented -j228 ohm and cost 3.4 dB for nothing. D1 is rotated onto the run at (171.30, 42.416) so pad 1 overlaps the line directly and pad 2 lands in the RF ground pour; the spur is deleted. Return loss, worst term first: SMA launch land 12.0 -> 30.0 dB (10.7 -> 37.0 ohm) D1 ESD clamp 19.2 -> 22.6 dB (now just the part's own 0.3 pF) C85 DNP tuning stub 25.5 dB unchanged, intentional provision C84 DNP land in line 30.1 dB unchanged, negligible worst-case coherent 7.0 -> 14.4 dB The dominant term is now a component choice rather than a layout defect. Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group, parity unchanged at the 402 pre-existing warnings, RF still 10 segments all on F.Cu at exactly 0.164 mm. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
Çıktılar
Bu klasör build/routing çalışma alanıdır. Repository'de yalnızca güncel ve anlamlı teslim çıktıları tutulur:
bom.csv: ayrıntılı mühendislik BOM'u.jlcpcb_bom.csv: montaj servisi için sadeleştirilmiş BOM.erc_final_reset.rpt: güncel şema ERC raporu; 0 ihlal.drc_final_placement.rpt: unrouted placement DRC raporu.drc_power_local.rpt: sinyal routing'inden önceki güç katı DRC raporu.drc_final_routed.rpt: routed kart DRC raporu.board_final_reset_top.png: güncel üst görünüm.
Routing çalışma dosyaları:
signal_stage.dsn/signal_stage.ses: autorouter'a verilen ve ondan alınan sinyal katı. Sadeceboard_power_local.kicad_pcbile birlikte anlamlıdır.signal_stage_preview.kicad_pcb: DSN'e giren bakırın KiCad'de incelenebilir hâli.freerouting_signal.log: pass başına unrouted/violation sayısı.
Eski .dsn, .ses, preview PCB ve ara DRC raporları yeni netlist için
authoritative değildir. .dsn her zaman onu üreten karta bağlıdır: placement,
güç bakırı veya keepout değiştiğinde export ve routing baştan yapılmalıdır,
yoksa import edilen sonuç mevcut bakırla çakışır.
Final routed raporda sıfır açık bağlantı, sıfır clearance/short ve sıfır
schematic-parity hatası hedeflenir. Unrouted aşamadaki unconnected_items,
via_dangling ve isolated_copper kayıtları normaldir: sırasıyla henüz
çekilmemiş bağlantıları, henüz kullanılmayan BGA escape via'larını ve final
fill'de silinecek plane parçalarını gösterir.