onur
af7c43b2a8
The Ti375 fanout could not be resolved with three routing layers, so L5 stops being a dedicated 1.8-V plane and becomes a signal layer. No rail owns a whole layer any more: the supplies are split into zone islands on L4 and L6, L2 and L7 stay solid and completely unrouted, and F.Cu, L3, L5 and B.Cu are all available for signals. Routing is staged rather than handed to the autorouter wholesale. The BGA escape, the buck high-current loops, plane stitching and the local power completion all run first and are locked; Freerouting then sees only the ordinary digital classes, with everything else present as fixed copper. finalize_routing.py installs the audited RF and USB geometry and closes whatever the autorouter left. Four bugs behind the routing failures, all of them the same shape - a layer list written down instead of read from the board, which was correct while L5 was a plane and silently wrong afterwards: - export_routing_stage.py emitted via keepouts for three layers only, so every existing via was invisible to the router on L5. It drove traces straight through them: 102 shorting_items in DRC. - route_local_power.py never used L5 at all, and picked up escape vias on two layers instead of all four. - add_rf_ground() judged fence positions against vias and pads but not tracks. It runs after the session import, when that region already has routed copper, and dropped a ground via on top of a signal trace. route_local_power.py also grew a via cloud on every rail: reaching a plane counted as progress even when it merged nothing, so the same pad collected a via per pass, 0.4 mm further out each time. Progress is now measured by the group count actually falling, and groups already sitting on their plane are skipped. That removed 404 redundant vias. The MAX2771 PLL loop filter was spread across three corners of the package, which forced the charge-pump node onto an inner layer under the GPS front end. All three parts now sit in the pocket at U21's north-west corner and the net stays on F.Cu. A permanent RF_NO_DIGITAL area plus a scoped rule keeps that region free of non-power copper on L3/L5/L6/B.Cu, and the local router enforces the same restriction, since it is the one stage that runs after the temporary keepout is deleted. Also enables the solder-mask bridge check that was switched off board-wide; the board passes it with no violations. Final board: DRC clean - no shorts, clearance, disallowed-item or dangling-copper violations - with 26 unconnected endpoints left. Routing is spread 37% L3, 27% F.Cu, 26% L5, 10% B.Cu over 6548 mm and 971 vias. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
98 lines
3.3 KiB
Python
98 lines
3.3 KiB
Python
#!/usr/bin/env python3
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"""Summarise what a routed board actually contains.
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DRC answers "is anything wrong"; this answers "is anything missing, and does
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the copper match the rules it was routed under". It reports the still-open
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connections per net, the track width actually used per net class (the Specctra
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round trip is where widths silently drift), the layer split, and the via count.
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"""
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from __future__ import annotations
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import argparse
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from collections import Counter, defaultdict
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from pathlib import Path
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import pcbnew
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def net_groups(board: pcbnew.BOARD, net: str) -> int:
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"""Count the separate copper islands a net is currently split into."""
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connectivity = board.GetConnectivity()
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pads = [pad for fp in board.GetFootprints() for pad in fp.Pads()
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if pad.GetNetname() == net]
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seen: set[str] = set()
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groups = 0
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for pad in pads:
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key = pad.m_Uuid.AsString()
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if key in seen:
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continue
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members = [item for item in connectivity.GetConnectedItems(pad, 0)
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if item.GetClass() == "PAD"]
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for item in members:
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seen.add(item.m_Uuid.AsString())
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seen.add(key)
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groups += 1
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return groups
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def main() -> None:
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parser = argparse.ArgumentParser()
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parser.add_argument("board", type=Path)
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args = parser.parse_args()
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board = pcbnew.LoadBoard(str(args.board))
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board.BuildConnectivity()
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net_class: dict[str, str] = {}
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pad_count: Counter[str] = Counter()
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for footprint in board.GetFootprints():
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for pad in footprint.Pads():
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name = pad.GetNetname()
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if name:
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net_class[name] = pad.GetNetClassName()
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pad_count[name] += 1
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widths: dict[str, Counter[float]] = defaultdict(Counter)
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layers: Counter[str] = Counter()
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vias = 0
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for item in board.GetTracks():
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if isinstance(item, pcbnew.PCB_VIA):
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vias += 1
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continue
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name = item.GetNetname()
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widths[net_class.get(name, "?")][round(pcbnew.ToMM(item.GetWidth()), 3)] += 1
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layers[board.GetLayerName(item.GetLayer())] += 1
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print(f"Board: {args.board}")
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print(f"Unconnected endpoints reported by connectivity: "
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f"{board.GetConnectivity().GetUnconnectedCount(True)}")
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print(f"Tracks: {sum(layers.values())} Vias: {vias}")
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print("\nTrack segments per layer:")
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for layer, count in layers.most_common():
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print(f" {layer:10s} {count:6d}")
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print("\nTrack width used per net class (mm: segments):")
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for klass in sorted(widths):
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used = ", ".join(f"{width}: {count}"
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for width, count in sorted(widths[klass].items()))
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print(f" {klass:12s} {used}")
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print("\nNets still split into more than one copper group:")
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incomplete = []
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for name in sorted(net_class):
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if pad_count[name] < 2:
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continue
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groups = net_groups(board, name)
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if groups > 1:
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incomplete.append((groups, name))
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for groups, name in sorted(incomplete, reverse=True):
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print(f" {name:22s} {net_class[name]:12s} "
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f"{pad_count[name]:3d} pads in {groups} groups")
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print(f" ({len(incomplete)} nets incomplete)" if incomplete
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else " none - every net is one connected group")
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if __name__ == "__main__":
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main()
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