onur
95609a6b6a
The board now routes end to end. Every net carrying two or more pads is a single connected copper group (216 nets, 1175 pads); kicad-cli reports 0 DRC violations and 0 unconnected items with zones refilled. Freerouting was never the blocker. The 14 remaining opens were three separate defects: 1. Obstacles in route_local_power.py modelled every pad as its axis-aligned bounding box. A 0.8-mm BGA dogbone site sits diagonally between four lands: true clearance 0.1407 mm, but the box test measured 0.4 mm from the box edge and rejected it, so no via could be placed anywhere in the Ti375 escape field. Replaced with an exact rounded-rectangle model, validated against KiCad's own SHAPE::Collide to 0.00 um over 14850 samples. Same 0 DRC and one fewer unconnected at the route_local_power stage. 2. CLOCK's 0.15-mm clearance cannot physically escape the BGA: two adjacent 0.45-mm dogbone vias on 0.8-mm pitch leave a 0.35-mm channel and a 0.10-mm trace needs 0.40 mm. HARD_TCK and MAX_SCLK could never leave the package. New rule "Ti375 escape field copper clearance" relaxes clearance to the 0.10 mm this field already uses, only where both objects are inside U1's courtyard. The clock trunk keeps 0.15 mm outside it. 3. RF_NO_DIGITAL was a rectangle reaching 7 mm past the RF line, covering the MAX2771's whole digital pin field and forcing every U21 output onto F.Cu alone. Narrowed to the corridor generate_pcb.py already reserves as TEMP_RF_LINE (y <= 43.7), clearing RF copper by 1.1 mm. The RF return path is guaranteed by the unrouted L2/L7 ground planes, not by this area. scripts/close_remaining.py replaces the ad-hoc residual scripts: a multi-layer maze over (x, y, layer) at 0.1 mm on all five routable layers, seeded from all copper of both groups, exact clearances, 0.10-mm necking inside the escape field, and reversible rip-up that rolls back entirely if a displaced net cannot be put back. ~150 s for the whole board. Also removes the regenerable intermediate boards, one-off session logs and the superseded residual scripts, and tracks board_routed.* as the deliverable. The 402 schematic-parity warnings are pre-existing and unchanged: 199 auto-named unconnected pins, 199 footprint library-nickname mismatches, and 4 mounting holes with no symbol. None affects connectivity or fabrication. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
Türetilmiş tasarım verileri
Bu klasördeki CSV/ISF dosyaları elle düzenlenecek ana tasarım kaynağı değildir;
scripts/design_data.py ve scripts/generate_design_tables.py üzerinden tekrar
üretilir.
Okunabilir tasarım dokümanları:
COMPONENT_SELECTION.md: ana IC seçimi, besleme ve kapasite sınırları.INTERFACES.md: RF, MAX2771, SafeSPI, QSPI, FTDI/USB ve test noktaları.FPGA_PINOUT.md: FPGA ball/bank/gerilim ve dört PMOD eşlemesi.POWER_TREE.md: giriş power-path, rail sıralaması, supervisor ve reset.
| Dosya | Açıklama |
|---|---|
ti375_c529_package.csv |
Efinity 2025.2 Ti375C529 paket veritabanından çıkarılmış 529 ball kaydı |
ti375_c529_package.meta.json |
Paket verisinin kaynak/sürüm metadatası |
ti375_pinout.csv |
Kartta kullanılan sinyal, ball, bank, VCCIO, I/O standardı ve konnektör eşlemesi |
unused_gpio_inventory.csv |
Kullanılan ve fiziksel olarak boş bırakılan fabric GPIO envanteri |
ti375_pin_constraints.isf |
HDL/Efinity tarafı için pin ve I/O standardı constraintleri |
max2771_registers.csv |
Kartın MAX2771 başlangıç register görüntüsü |
Yeniden üretmek için:
python3 scripts/generate_design_tables.py
Script aşağıdaki koşulları doğrular:
- Paket kaynağında tam 529 benzersiz ball bulunması.
- Dedicated TCK/TMS/TDI/TDO, CRESET_N, CDONE ve JTAG_VCCIO_SEL adları.
- Seçilen bankın istenen 3.3 V, 3.0 V veya 1.8 V I/O standardını desteklemesi.
- PMOD tahsislerinde konfigürasyon/PLL/clock özel fonksiyonlarının yanlışlıkla kullanılmaması.
- MAX2771 ve SCH16T için ayrılmış pinlerle PMOD çakışması olmaması.
Hard JTAG yalnızca kart üzerindeki FT4232H interface 1 üzerinden erişilir;
harici ARM/JTAG headerı yoktur. FPGA_CRESET_N, açık-drenç power/FTDI/harici
reset fan-in'i olarak belgelenmiştir.