max2771 spi liens has been added.
This commit is contained in:
onur
@@ -0,0 +1,13 @@
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QUESTA ?=
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VLOG := $(if $(QUESTA),$(QUESTA)/bin/)vlog
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VSIM := $(if $(QUESTA),$(QUESTA)/bin/)vsim
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WORK := work
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.PHONY: test clean
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test: clean
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$(VLOG) -sv -work $(WORK) rtl/max2771_spi_engine.sv tb/max2771_spi_engine_tb.sv
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$(VSIM) -c -work $(WORK) max2771_spi_engine_tb -do "run -all; quit -f"
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clean:
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rm -rf $(WORK) transcript vsim.wlf
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@@ -0,0 +1,66 @@
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# MAX2771 Three-Wire SPI IP
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This directory contains the dedicated MAX2771 serial engine. It is independent
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of the generic `pmod_spi` controller and implements the MAX2771 transaction
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format directly.
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Primary references:
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- [MAX2771 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/max2771.pdf), Serial Interface and Table 15
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- [MAX2771 EV kit data sheet and schematic](https://www.analog.com/media/en/technical-documentation/data-sheets/MAX2771EVKIT.pdf)
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## Protocol
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Every command is one 48-SCLK frame while `CSN` is low:
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```text
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clocks 0..11 A[11:0], MSB first; A[11:4] are zero
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clock 12 R/W: 1 read, 0 write
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clocks 13..15 three turnaround clocks
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clocks 16..47 D[31:0], MSB first
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```
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`SCLK` idles low. Both sides sample on rising edges and change data on falling
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edges. `SDATA` is one bidirectional line, not separate MOSI and MISO signals.
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For reads, the host releases `SDATA` on the falling edge after the R/W bit and
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keeps it as an input through the three turnaround clocks and 32 data clocks.
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The divider uses ceiling division so SCLK never exceeds the 4 MHz data-sheet
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limit:
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```text
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board fabric clock half-period SCLK period
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Genesys 2 50 MHz 7 cycles 3.571 MHz 280 ns
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VCU118 100 MHz 13 cycles 3.846 MHz 260 ns
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```
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Both satisfy the 250 ns minimum period. The engine also enforces at least one
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half-period for CS setup and hold and at least 100 ns between transactions.
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## MMIO
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The TileLink wrapper is at `0x10016000` on both FPGA targets.
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| Offset | Name | Description |
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| --- | --- | --- |
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| `0x00` | COMMAND | bits 3:0 address, bit 8 read; write starts a frame |
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| `0x04` | WRITE_DATA | 32-bit register write value |
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| `0x08` | READ_DATA | last 32-bit register read value |
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| `0x0c` | STATUS | bit 0 ready, bit 1 busy |
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| `0x10` | INPUT_CLOCK_HZ | configured board fabric clock |
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| `0x14` | SCLK_HZ | actual divided serial clock |
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| `0x18` | HALF_PERIOD | fabric cycles per SCLK half-period |
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| `0x1c` | IDENT | `0x4d415831` (`MAX1`) |
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## Simulation
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The self-checking testbench models the MAX2771 side of the resolved SDATA wire
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and covers writes, reads, turnaround high impedance, contention, frame order,
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frame length, CS timing, and both board clock parameters.
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```bash
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make -C hardware/ip/max2771_spi test
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```
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This target uses `vlog` and `vsim`. Set `QUESTA=/path/to/questa` when they are
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not on `PATH`.
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@@ -0,0 +1,104 @@
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`timescale 1ns/1ps
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module max2771_spi_engine #(
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parameter integer CLOCK_HZ = 50_000_000,
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parameter integer MAX_SCLK_HZ = 4_000_000
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) (
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input wire clk,
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input wire rst_n,
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input wire start,
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input wire read_not_write,
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input wire [3:0] address,
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input wire [31:0] write_data,
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output reg [31:0] read_data,
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output reg busy,
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output wire ready,
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output reg sclk,
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output reg csn,
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input wire sdata_i,
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output reg sdata_o,
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output reg sdata_oe
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);
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// Ceiling division keeps SCLK at or below the MAX2771 4 MHz limit.
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localparam integer HALF_PERIOD_CYCLES =
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(CLOCK_HZ + (2 * MAX_SCLK_HZ) - 1) / (2 * MAX_SCLK_HZ);
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localparam integer CS_INACTIVE_CYCLES =
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(CLOCK_HZ + 10_000_000 - 1) / 10_000_000;
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reg [47:0] tx_shift;
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reg [31:0] rx_shift;
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reg [5:0] bit_index;
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integer half_count;
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integer inactive_count;
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reg transaction_is_read;
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assign ready = !busy && (inactive_count == 0);
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initial begin
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if (CLOCK_HZ <= 0)
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$error("CLOCK_HZ must be positive");
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if (MAX_SCLK_HZ <= 0)
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$error("MAX_SCLK_HZ must be positive");
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if (HALF_PERIOD_CYCLES < 1)
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$error("HALF_PERIOD_CYCLES must be at least one");
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end
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always @(posedge clk) begin
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if (!rst_n) begin
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read_data <= 32'd0;
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busy <= 1'b0;
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sclk <= 1'b0;
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csn <= 1'b1;
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sdata_o <= 1'b0;
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sdata_oe <= 1'b0;
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tx_shift <= 48'd0;
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rx_shift <= 32'd0;
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bit_index <= 6'd0;
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half_count <= 0;
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inactive_count <= 0;
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transaction_is_read <= 1'b0;
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end else if (busy) begin
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if (half_count != 0) begin
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half_count <= half_count - 1;
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end else begin
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half_count <= HALF_PERIOD_CYCLES - 1;
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if (!sclk) begin
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// MAX2771 samples input and the host samples read data on rising SCLK.
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sclk <= 1'b1;
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if (transaction_is_read && (bit_index >= 6'd16))
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rx_shift <= {rx_shift[30:0], sdata_i};
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end else begin
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// Both sides change or release SDATA on falling SCLK.
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sclk <= 1'b0;
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if (bit_index == 6'd47) begin
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read_data <= rx_shift;
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busy <= 1'b0;
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csn <= 1'b1;
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sdata_oe <= 1'b0;
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inactive_count <= CS_INACTIVE_CYCLES;
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end else begin
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bit_index <= bit_index + 1'b1;
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tx_shift <= {tx_shift[46:0], 1'b0};
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sdata_o <= tx_shift[46];
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if (transaction_is_read && (bit_index == 6'd12))
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sdata_oe <= 1'b0;
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end
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end
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end
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end else if (inactive_count != 0) begin
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inactive_count <= inactive_count - 1;
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end else if (start) begin
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// Frame: A[11:0], R/W, three turnaround bits, D[31:0]. A[11:4] are zero.
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tx_shift <= {8'd0, address, read_not_write, 3'd0, write_data};
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rx_shift <= 32'd0;
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bit_index <= 6'd0;
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transaction_is_read <= read_not_write;
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busy <= 1'b1;
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csn <= 1'b0;
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sclk <= 1'b0;
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sdata_o <= 1'b0;
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sdata_oe <= 1'b1;
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half_count <= HALF_PERIOD_CYCLES - 1;
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end
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end
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endmodule
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@@ -0,0 +1,251 @@
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`timescale 1ns/1ps
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module max2771_spi_engine_case #(
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parameter integer CLOCK_HZ = 50_000_000,
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parameter integer CLOCK_PERIOD_NS = 20,
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parameter integer EXPECTED_HALF_CYCLES = 7
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) (
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output reg done,
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output reg failed
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);
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localparam [31:0] READ_VALUE = 32'hA596_3CC3;
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localparam [31:0] WRITE_VALUE = 32'hBEA4_1603;
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localparam realtime EXPECTED_HALF_NS = CLOCK_PERIOD_NS * EXPECTED_HALF_CYCLES;
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reg clk = 1'b0;
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reg rst_n = 1'b0;
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reg start = 1'b0;
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reg read_not_write = 1'b0;
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reg [3:0] address = 4'd0;
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reg [31:0] write_data = 32'd0;
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wire [31:0] read_data;
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wire busy;
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wire ready;
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wire sclk;
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wire csn;
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wire sdata_i;
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wire sdata_o;
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wire sdata_oe;
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tri sdata;
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reg slave_oe = 1'b0;
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reg slave_data = 1'b0;
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realtime previous_sclk_edge;
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realtime csn_assert_time;
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realtime last_rising_time;
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realtime previous_csn_release;
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integer edge_count;
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assign sdata = sdata_oe ? sdata_o : 1'bz;
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assign sdata = slave_oe ? slave_data : 1'bz;
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assign sdata_i = sdata;
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max2771_spi_engine #(
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.CLOCK_HZ(CLOCK_HZ),
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.MAX_SCLK_HZ(4_000_000)
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) dut (
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.clk(clk),
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.rst_n(rst_n),
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.start(start),
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.read_not_write(read_not_write),
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.address(address),
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.write_data(write_data),
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.read_data(read_data),
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.busy(busy),
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.ready(ready),
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.sclk(sclk),
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.csn(csn),
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.sdata_i(sdata_i),
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.sdata_o(sdata_o),
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.sdata_oe(sdata_oe)
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);
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always #(CLOCK_PERIOD_NS / 2.0) clk = ~clk;
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task automatic fail(input string message);
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begin
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$error("CLOCK_HZ=%0d: %s", CLOCK_HZ, message);
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failed = 1'b1;
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end
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endtask
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task automatic check(input bit condition, input string message);
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begin
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if (!condition)
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fail(message);
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end
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endtask
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task automatic launch(
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input bit is_read,
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input [3:0] register_address,
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input [31:0] value
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);
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begin
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wait (ready);
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@(negedge clk);
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read_not_write = is_read;
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address = register_address;
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write_data = value;
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start = 1'b1;
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@(negedge clk);
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start = 1'b0;
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wait (!csn);
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end
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endtask
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task automatic check_edge_timing(input realtime now_time);
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realtime delta;
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begin
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if (edge_count != 0) begin
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delta = now_time - previous_sclk_edge;
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if (delta != EXPECTED_HALF_NS)
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fail($sformatf("SCLK half-period %0.3f ns, expected %0.3f ns",
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delta, EXPECTED_HALF_NS));
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end
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previous_sclk_edge = now_time;
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edge_count = edge_count + 1;
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end
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endtask
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task automatic run_write;
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reg [47:0] expected_frame;
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integer bit_number;
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begin
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expected_frame = {8'd0, 4'h0, 1'b0, 3'd0, WRITE_VALUE};
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edge_count = 0;
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launch(1'b0, 4'h0, WRITE_VALUE);
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csn_assert_time = $realtime;
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if (previous_csn_release != 0.0)
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check((csn_assert_time - previous_csn_release) >= 100.0,
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"CSN inactive interval is shorter than 100 ns");
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for (bit_number = 0; bit_number < 48; bit_number = bit_number + 1) begin
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@(posedge sclk);
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check_edge_timing($realtime);
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if (bit_number == 0)
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check(($realtime - csn_assert_time) >= 10.0,
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"CSN setup is shorter than 10 ns");
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check(sdata_oe === 1'b1, "host released SDATA during write frame");
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check(sdata === expected_frame[47-bit_number],
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$sformatf("write frame mismatch at bit %0d", bit_number));
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check(sdata !== 1'bx, "SDATA contention detected during write");
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last_rising_time = $realtime;
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@(negedge sclk);
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check_edge_timing($realtime);
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end
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#1;
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check(csn === 1'b1, "CSN did not deassert after 48 clocks");
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check(sdata_oe === 1'b0, "host did not release SDATA after write");
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check(($realtime - 1.0 - last_rising_time) >= 10.0,
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"CSN hold is shorter than 10 ns");
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previous_csn_release = $realtime - 1.0;
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end
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endtask
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task automatic run_read;
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reg [47:0] expected_header;
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integer bit_number;
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begin
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expected_header = {8'd0, 4'h9, 1'b1, 3'd0, 32'd0};
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edge_count = 0;
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launch(1'b1, 4'h9, 32'd0);
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csn_assert_time = $realtime;
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check((csn_assert_time - previous_csn_release) >= 100.0,
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"CSN inactive interval is shorter than 100 ns");
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for (bit_number = 0; bit_number < 48; bit_number = bit_number + 1) begin
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@(posedge sclk);
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check_edge_timing($realtime);
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if (bit_number <= 12) begin
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check(sdata_oe === 1'b1,
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$sformatf("host released SDATA in read header at bit %0d", bit_number));
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check(sdata === expected_header[47-bit_number],
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$sformatf("read header mismatch at bit %0d", bit_number));
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end else if (bit_number <= 15) begin
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check(sdata_oe === 1'b0, "host drove SDATA during turnaround");
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check(slave_oe === 1'b0, "slave drove SDATA during turnaround");
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check(sdata === 1'bz, "SDATA was not high impedance during turnaround");
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end else begin
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check(sdata_oe === 1'b0, "host drove SDATA during read data");
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check(slave_oe === 1'b1, "slave did not drive read data");
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check(sdata === READ_VALUE[47-bit_number],
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$sformatf("read data mismatch at bit %0d", bit_number));
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check(sdata !== 1'bx, "SDATA contention detected during read");
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end
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last_rising_time = $realtime;
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@(negedge sclk);
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check_edge_timing($realtime);
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if ((bit_number >= 15) && (bit_number < 47)) begin
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slave_oe = 1'b1;
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slave_data = READ_VALUE[46-bit_number];
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end
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end
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slave_oe = 1'b0;
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#1;
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check(csn === 1'b1, "CSN did not deassert after read frame");
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check(read_data === READ_VALUE,
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$sformatf("read result 0x%08x, expected 0x%08x", read_data, READ_VALUE));
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check(sdata_oe === 1'b0, "host did not keep SDATA as input after read");
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previous_csn_release = $realtime - 1.0;
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end
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endtask
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initial begin
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done = 1'b0;
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failed = 1'b0;
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previous_csn_release = 0.0;
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repeat (5) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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check(ready === 1'b1, "engine was not ready after reset");
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check(csn === 1'b1, "CSN was not idle high after reset");
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check(sclk === 1'b0, "SCLK was not idle low after reset");
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check(sdata_oe === 1'b0, "SDATA was not an input after reset");
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run_write();
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run_read();
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done = 1'b1;
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end
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endmodule
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module max2771_spi_engine_tb;
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wire done_50mhz;
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wire failed_50mhz;
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wire done_100mhz;
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wire failed_100mhz;
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max2771_spi_engine_case #(
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.CLOCK_HZ(50_000_000),
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.CLOCK_PERIOD_NS(20),
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.EXPECTED_HALF_CYCLES(7)
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) case_50mhz (
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.done(done_50mhz),
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.failed(failed_50mhz)
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);
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max2771_spi_engine_case #(
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.CLOCK_HZ(100_000_000),
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.CLOCK_PERIOD_NS(10),
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.EXPECTED_HALF_CYCLES(13)
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) case_100mhz (
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.done(done_100mhz),
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.failed(failed_100mhz)
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);
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initial begin
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wait (done_50mhz && done_100mhz);
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if (failed_50mhz || failed_100mhz)
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$fatal(1, "MAX2771 SPI engine test FAILED");
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$display("MAX2771 SPI engine test PASSED: 50 MHz -> 3.571 MHz, 100 MHz -> 3.846 MHz");
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$finish;
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end
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initial begin
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#100_000;
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$fatal(1, "MAX2771 SPI engine test timed out");
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end
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endmodule
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Reference in New Issue
Block a user