Files
gps/hardware/generated/genesys2-soc-verilog/TLError.sv
T
2026-08-06 22:14:52 +03:00

87 lines
3.3 KiB
Systemverilog

// Generated by CIRCT firtool-1.151.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module TLError(
input clock,
reset,
output auto_in_a_ready,
input auto_in_a_valid,
input [2:0] auto_in_a_bits_opcode,
auto_in_a_bits_param,
input [3:0] auto_in_a_bits_size,
input [1:0] auto_in_a_bits_source,
input [13:0] auto_in_a_bits_address,
input [7:0] auto_in_a_bits_mask,
input [63:0] auto_in_a_bits_data,
input auto_in_a_bits_corrupt,
auto_in_d_ready,
output auto_in_d_valid,
output [2:0] auto_in_d_bits_opcode,
output [3:0] auto_in_d_bits_size,
output [1:0] auto_in_d_bits_source,
output auto_in_d_bits_corrupt
);
wire [2:0] da_bits_opcode;
wire _a_q_io_deq_valid;
wire [2:0] _a_q_io_deq_bits_opcode;
wire [3:0] _a_q_io_deq_bits_size;
wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
wire [26:0] _GEN_0 = {23'h0, _a_q_io_deq_bits_size};
wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _GEN_0;
wire [8:0] a_last_beats1 =
_a_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_a_last_beats1_decode_T[11:3]);
reg [8:0] a_last_counter;
wire a_last = a_last_counter == 9'h1 | a_last_beats1 == 9'h0;
wire [26:0] _r_beats1_decode_T = 27'hFFF << _GEN_0;
wire [8:0] r_beats1 = da_bits_opcode[0] ? ~(_r_beats1_decode_T[11:3]) : 9'h0;
reg [8:0] r_counter;
wire a_q_io_deq_ready =
auto_in_d_ready & (r_counter == 9'h1 | r_beats1 == 9'h0) | ~a_last;
wire da_valid = _a_q_io_deq_valid & a_last;
assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode];
always @(posedge clock) begin
if (reset) begin
a_last_counter <= 9'h0;
r_counter <= 9'h0;
end
else begin
if (a_q_io_deq_ready & _a_q_io_deq_valid)
a_last_counter <= a_last_counter == 9'h0 ? a_last_beats1 : a_last_counter - 9'h1;
if (auto_in_d_ready & da_valid)
r_counter <= r_counter == 9'h0 ? r_beats1 : r_counter - 9'h1;
end
end // always @(posedge)
Queue1_TLBundleA_a14d64s2k1z4u a_q (
.clock (clock),
.reset (reset),
.io_enq_ready (auto_in_a_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (a_q_io_deq_ready),
.io_deq_valid (_a_q_io_deq_valid),
.io_deq_bits_opcode (_a_q_io_deq_bits_opcode),
.io_deq_bits_size (_a_q_io_deq_bits_size),
.io_deq_bits_source (auto_in_d_bits_source)
);
assign auto_in_d_valid = da_valid;
assign auto_in_d_bits_opcode = da_bits_opcode;
assign auto_in_d_bits_size = _a_q_io_deq_bits_size;
assign auto_in_d_bits_corrupt = da_bits_opcode[0];
endmodule