onur
61 lines
2.4 KiB
Systemverilog
61 lines
2.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module CLINTClockSinkDomain(
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output auto_clint_in_a_ready,
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input auto_clint_in_a_valid,
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input [2:0] auto_clint_in_a_bits_opcode,
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input [1:0] auto_clint_in_a_bits_size,
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input [5:0] auto_clint_in_a_bits_source,
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input [25:0] auto_clint_in_a_bits_address,
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input [7:0] auto_clint_in_a_bits_mask,
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input [63:0] auto_clint_in_a_bits_data,
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input auto_clint_in_d_ready,
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output auto_clint_in_d_valid,
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output [2:0] auto_clint_in_d_bits_opcode,
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output [1:0] auto_clint_in_d_bits_size,
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output [5:0] auto_clint_in_d_bits_source,
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output [63:0] auto_clint_in_d_bits_data,
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output auto_int_in_clock_xing_out_sync_0,
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auto_int_in_clock_xing_out_sync_1,
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input auto_clock_in_clock,
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auto_clock_in_reset,
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tick,
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output clock,
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reset
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);
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wire _clint_auto_int_out_0;
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wire _clint_auto_int_out_1;
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CLINT clint (
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.clock (auto_clock_in_clock),
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.reset (auto_clock_in_reset),
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.auto_int_out_0 (_clint_auto_int_out_0),
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.auto_int_out_1 (_clint_auto_int_out_1),
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.auto_in_a_ready (auto_clint_in_a_ready),
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.auto_in_a_valid (auto_clint_in_a_valid),
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.auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode),
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.auto_in_a_bits_size (auto_clint_in_a_bits_size),
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.auto_in_a_bits_source (auto_clint_in_a_bits_source),
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.auto_in_a_bits_address (auto_clint_in_a_bits_address),
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.auto_in_a_bits_mask (auto_clint_in_a_bits_mask),
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.auto_in_a_bits_data (auto_clint_in_a_bits_data),
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.auto_in_d_ready (auto_clint_in_d_ready),
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.auto_in_d_valid (auto_clint_in_d_valid),
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.auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode),
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.auto_in_d_bits_size (auto_clint_in_d_bits_size),
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.auto_in_d_bits_source (auto_clint_in_d_bits_source),
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.auto_in_d_bits_data (auto_clint_in_d_bits_data),
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.io_rtcTick (tick)
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);
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IntSyncCrossingSource_n1x2 intsource (
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.clock (auto_clock_in_clock),
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.reset (auto_clock_in_reset),
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.auto_in_0 (_clint_auto_int_out_0),
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.auto_in_1 (_clint_auto_int_out_1),
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.auto_out_sync_0 (auto_int_in_clock_xing_out_sync_0),
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.auto_out_sync_1 (auto_int_in_clock_xing_out_sync_1)
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);
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assign clock = auto_clock_in_clock;
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assign reset = auto_clock_in_reset;
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endmodule
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