onur
67 lines
2.4 KiB
Markdown
67 lines
2.4 KiB
Markdown
# MAX2771 Three-Wire SPI IP
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This directory contains the dedicated MAX2771 serial engine. It is independent
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of the generic `pmod_spi` controller and implements the MAX2771 transaction
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format directly.
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Primary references:
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- [MAX2771 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/max2771.pdf), Serial Interface and Table 15
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- [MAX2771 EV kit data sheet and schematic](https://www.analog.com/media/en/technical-documentation/data-sheets/MAX2771EVKIT.pdf)
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## Protocol
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Every command is one 48-SCLK frame while `CSN` is low:
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```text
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clocks 0..11 A[11:0], MSB first; A[11:4] are zero
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clock 12 R/W: 1 read, 0 write
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clocks 13..15 three turnaround clocks
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clocks 16..47 D[31:0], MSB first
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```
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`SCLK` idles low. Both sides sample on rising edges and change data on falling
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edges. `SDATA` is one bidirectional line, not separate MOSI and MISO signals.
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For reads, the host releases `SDATA` on the falling edge after the R/W bit and
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keeps it as an input through the three turnaround clocks and 32 data clocks.
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The divider uses ceiling division so SCLK never exceeds the 4 MHz data-sheet
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limit:
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```text
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board fabric clock half-period SCLK period
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Genesys 2 50 MHz 7 cycles 3.571 MHz 280 ns
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VCU118 100 MHz 13 cycles 3.846 MHz 260 ns
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```
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Both satisfy the 250 ns minimum period. The engine also enforces at least one
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half-period for CS setup and hold and at least 100 ns between transactions.
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## MMIO
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The TileLink wrapper is at `0x10016000` on both FPGA targets.
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| Offset | Name | Description |
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| --- | --- | --- |
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| `0x00` | COMMAND | bits 3:0 address, bit 8 read; write starts a frame |
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| `0x04` | WRITE_DATA | 32-bit register write value |
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| `0x08` | READ_DATA | last 32-bit register read value |
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| `0x0c` | STATUS | bit 0 ready, bit 1 busy |
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| `0x10` | INPUT_CLOCK_HZ | configured board fabric clock |
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| `0x14` | SCLK_HZ | actual divided serial clock |
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| `0x18` | HALF_PERIOD | fabric cycles per SCLK half-period |
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| `0x1c` | IDENT | `0x4d415831` (`MAX1`) |
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## Simulation
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The self-checking testbench models the MAX2771 side of the resolved SDATA wire
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and covers writes, reads, turnaround high impedance, contention, frame order,
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frame length, CS timing, and both board clock parameters.
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```bash
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make -C hardware/ip/max2771_spi test
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```
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This target uses `vlog` and `vsim`. Set `QUESTA=/path/to/questa` when they are
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not on `PATH`.
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