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gps/hardware/generated/genesys2-soc-verilog/Arbiter3_LLWB.sv
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2026-08-06 22:14:52 +03:00

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Systemverilog

// Generated by CIRCT firtool-1.151.0
module Arbiter3_LLWB(
output io_in_0_ready,
input io_in_0_valid,
input [63:0] io_in_0_bits_data,
input [4:0] io_in_0_bits_tag,
input io_out_ready,
output io_out_valid,
output [63:0] io_out_bits_data,
output [4:0] io_out_bits_tag
);
assign io_in_0_ready = io_out_ready;
assign io_out_valid = io_in_0_valid;
assign io_out_bits_data = io_in_0_valid ? io_in_0_bits_data : 64'h0;
assign io_out_bits_tag = io_in_0_valid ? io_in_0_bits_tag : 5'h0;
endmodule