19 lines
549 B
Systemverilog
19 lines
549 B
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module Arbiter3_LLWB(
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output io_in_0_ready,
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input io_in_0_valid,
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input [63:0] io_in_0_bits_data,
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input [4:0] io_in_0_bits_tag,
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input io_out_ready,
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output io_out_valid,
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output [63:0] io_out_bits_data,
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output [4:0] io_out_bits_tag
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);
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assign io_in_0_ready = io_out_ready;
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assign io_out_valid = io_in_0_valid;
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assign io_out_bits_data = io_in_0_valid ? io_in_0_bits_data : 64'h0;
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assign io_out_bits_tag = io_in_0_valid ? io_in_0_bits_tag : 5'h0;
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endmodule
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