onur
726 lines
38 KiB
Systemverilog
726 lines
38 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module FPU(
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input clock,
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reset,
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input [31:0] io_inst,
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input [63:0] io_fromint_data,
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input [2:0] io_fcsr_rm,
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output io_fcsr_flags_valid,
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output [4:0] io_fcsr_flags_bits,
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output [63:0] io_store_data,
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io_toint_data,
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input io_ll_resp_val,
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input [2:0] io_ll_resp_type,
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input [4:0] io_ll_resp_tag,
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input [63:0] io_ll_resp_data,
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input io_valid,
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output io_fcsr_rdy,
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io_nack_mem,
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io_illegal_rm,
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input io_killx,
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io_killm,
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output io_dec_wen,
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io_dec_ren1,
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io_dec_ren2,
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io_dec_ren3,
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io_sboard_set,
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io_sboard_clr,
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output [4:0] io_sboard_clra
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);
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wire divSqrt_inFlight;
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wire [4:0] divSqrt_flags;
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wire [64:0] divSqrt_wdata;
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wire divSqrt_wen;
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wire divSqrt_typeTag;
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wire _divSqrt_1_io_inReady;
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wire _divSqrt_1_io_outValid_div;
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wire _divSqrt_1_io_outValid_sqrt;
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wire [64:0] _divSqrt_1_io_out;
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wire [4:0] _divSqrt_1_io_exceptionFlags;
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wire _divSqrt_io_inReady;
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wire _divSqrt_io_outValid_div;
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wire _divSqrt_io_outValid_sqrt;
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wire [32:0] _divSqrt_io_out;
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wire [4:0] _divSqrt_io_exceptionFlags;
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wire [64:0] _dfma_io_out_bits_data;
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wire [4:0] _dfma_io_out_bits_exc;
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wire [64:0] _fpmu_io_out_bits_data;
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wire [4:0] _fpmu_io_out_bits_exc;
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wire [64:0] _ifpu_io_out_bits_data;
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wire [4:0] _ifpu_io_out_bits_exc;
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wire [2:0] _fpiu_io_out_bits_in_rm;
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wire [64:0] _fpiu_io_out_bits_in_in1;
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wire [64:0] _fpiu_io_out_bits_in_in2;
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wire _fpiu_io_out_bits_lt;
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wire [4:0] _fpiu_io_out_bits_exc;
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wire [64:0] _sfma_io_out_bits_data;
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wire [4:0] _sfma_io_out_bits_exc;
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wire [64:0] _regfile_ext_R0_data;
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wire [64:0] _regfile_ext_R1_data;
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wire [64:0] _regfile_ext_R2_data;
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wire _fp_decoder_io_sigs_ren1;
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wire _fp_decoder_io_sigs_ren2;
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wire _fp_decoder_io_sigs_ren3;
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wire _fp_decoder_io_sigs_swap12;
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wire _fp_decoder_io_sigs_swap23;
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wire [1:0] _fp_decoder_io_sigs_typeTagIn;
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wire [1:0] _fp_decoder_io_sigs_typeTagOut;
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wire _fp_decoder_io_sigs_fromint;
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wire _fp_decoder_io_sigs_toint;
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wire _fp_decoder_io_sigs_fastpipe;
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wire _fp_decoder_io_sigs_fma;
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wire _fp_decoder_io_sigs_div;
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wire _fp_decoder_io_sigs_sqrt;
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wire _fp_decoder_io_sigs_wflags;
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reg ex_reg_valid;
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reg [31:0] ex_reg_inst;
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reg ex_reg_ctrl_ren2;
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reg ex_reg_ctrl_ren3;
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reg ex_reg_ctrl_swap23;
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reg [1:0] ex_reg_ctrl_typeTagIn;
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reg [1:0] ex_reg_ctrl_typeTagOut;
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reg ex_reg_ctrl_fromint;
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reg ex_reg_ctrl_toint;
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reg ex_reg_ctrl_fastpipe;
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reg ex_reg_ctrl_fma;
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reg ex_reg_ctrl_div;
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reg ex_reg_ctrl_sqrt;
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reg ex_reg_ctrl_wflags;
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reg [4:0] ex_ra_0;
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reg [4:0] ex_ra_1;
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reg [4:0] ex_ra_2;
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reg load_wb;
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reg [1:0] load_wb_typeTag;
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reg [63:0] load_wb_data;
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reg [4:0] load_wb_tag;
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reg mem_reg_valid;
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reg [31:0] mem_reg_inst;
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reg wb_reg_valid;
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reg [1:0] mem_ctrl_typeTagOut;
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reg mem_ctrl_fromint;
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reg mem_ctrl_toint;
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reg mem_ctrl_fastpipe;
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reg mem_ctrl_fma;
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reg mem_ctrl_div;
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reg mem_ctrl_sqrt;
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reg mem_ctrl_wflags;
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reg wb_ctrl_toint;
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wire [63:0] _wdata_T_2 =
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(load_wb_typeTag[0] ? 64'h0 : 64'hFFFFFFFF00000000) | load_wb_data;
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wire wdata_rawIn_isZeroExpIn = _wdata_T_2[62:52] == 11'h0;
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wire _wdata_rawIn_out_isNaN_T = |(_wdata_T_2[51:0]);
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wire [5:0] wdata_rawIn_normDist =
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_wdata_T_2[51]
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? 6'h0
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: _wdata_T_2[50]
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? 6'h1
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: _wdata_T_2[49]
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? 6'h2
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: _wdata_T_2[48]
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? 6'h3
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: _wdata_T_2[47]
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? 6'h4
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: _wdata_T_2[46]
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? 6'h5
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: _wdata_T_2[45]
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? 6'h6
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: _wdata_T_2[44]
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? 6'h7
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: _wdata_T_2[43]
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? 6'h8
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: _wdata_T_2[42]
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? 6'h9
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: _wdata_T_2[41]
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? 6'hA
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: _wdata_T_2[40]
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? 6'hB
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: _wdata_T_2[39]
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? 6'hC
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: _wdata_T_2[38]
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? 6'hD
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: _wdata_T_2[37]
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? 6'hE
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: _wdata_T_2[36]
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? 6'hF
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: _wdata_T_2[35]
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? 6'h10
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: _wdata_T_2[34]
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? 6'h11
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: _wdata_T_2[33]
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? 6'h12
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: _wdata_T_2[32]
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? 6'h13
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: _wdata_T_2[31]
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? 6'h14
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: _wdata_T_2[30]
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? 6'h15
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: _wdata_T_2[29]
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? 6'h16
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: _wdata_T_2[28]
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? 6'h17
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: _wdata_T_2[27]
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? 6'h18
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: _wdata_T_2[26]
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? 6'h19
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: _wdata_T_2[25]
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? 6'h1A
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: _wdata_T_2[24]
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? 6'h1B
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: _wdata_T_2[23]
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? 6'h1C
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: _wdata_T_2[22]
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? 6'h1D
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: _wdata_T_2[21]
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? 6'h1E
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: _wdata_T_2[20]
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? 6'h1F
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: _wdata_T_2[19]
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? 6'h20
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: _wdata_T_2[18]
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? 6'h21
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: _wdata_T_2[17]
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? 6'h22
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: _wdata_T_2[16]
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? 6'h23
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: _wdata_T_2[15]
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? 6'h24
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: _wdata_T_2[14]
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? 6'h25
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: _wdata_T_2[13]
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? 6'h26
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: _wdata_T_2[12]
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? 6'h27
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: _wdata_T_2[11]
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? 6'h28
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: _wdata_T_2[10]
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? 6'h29
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: _wdata_T_2[9]
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? 6'h2A
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: _wdata_T_2[8]
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? 6'h2B
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: _wdata_T_2[7]
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? 6'h2C
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: _wdata_T_2[6]
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? 6'h2D
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: _wdata_T_2[5]
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? 6'h2E
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: _wdata_T_2[4]
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? 6'h2F
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: _wdata_T_2[3]
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? 6'h30
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: _wdata_T_2[2]
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? 6'h31
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: {5'h19,
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~(_wdata_T_2[1])};
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wire [114:0] _wdata_rawIn_subnormFract_T =
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{63'h0, _wdata_T_2[51:0]} << wdata_rawIn_normDist;
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wire [11:0] _wdata_rawIn_adjustedExp_T_4 =
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(wdata_rawIn_isZeroExpIn ? {6'h3F, ~wdata_rawIn_normDist} : {1'h0, _wdata_T_2[62:52]})
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+ {10'h100, wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1};
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wire [51:0] _wdata_T_10 =
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wdata_rawIn_isZeroExpIn
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? {_wdata_rawIn_subnormFract_T[50:0], 1'h0}
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: _wdata_T_2[51:0];
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wire [2:0] _wdata_T_4 =
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wdata_rawIn_isZeroExpIn & ~_wdata_rawIn_out_isNaN_T
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? 3'h0
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: _wdata_rawIn_adjustedExp_T_4[11:9];
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wire _GEN =
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_wdata_T_4[0] | (&(_wdata_rawIn_adjustedExp_T_4[11:10])) & _wdata_rawIn_out_isNaN_T;
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wire wdata_rawIn_isZeroExpIn_1 = _wdata_T_2[30:23] == 8'h0;
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wire _wdata_rawIn_out_isNaN_T_2 = |(_wdata_T_2[22:0]);
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wire [4:0] wdata_rawIn_normDist_1 =
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_wdata_T_2[22]
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? 5'h0
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: _wdata_T_2[21]
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? 5'h1
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: _wdata_T_2[20]
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? 5'h2
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: _wdata_T_2[19]
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? 5'h3
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: _wdata_T_2[18]
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? 5'h4
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: _wdata_T_2[17]
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? 5'h5
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: _wdata_T_2[16]
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? 5'h6
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: _wdata_T_2[15]
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? 5'h7
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: _wdata_T_2[14]
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? 5'h8
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: _wdata_T_2[13]
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? 5'h9
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: _wdata_T_2[12]
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? 5'hA
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: _wdata_T_2[11]
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? 5'hB
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: _wdata_T_2[10]
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? 5'hC
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: _wdata_T_2[9]
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? 5'hD
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: _wdata_T_2[8]
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? 5'hE
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: _wdata_T_2[7]
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? 5'hF
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: _wdata_T_2[6]
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? 5'h10
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: _wdata_T_2[5]
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? 5'h11
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: _wdata_T_2[4]
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? 5'h12
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: _wdata_T_2[3]
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? 5'h13
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: _wdata_T_2[2]
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? 5'h14
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: _wdata_T_2[1]
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? 5'h15
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: 5'h16;
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wire [53:0] _wdata_rawIn_subnormFract_T_2 =
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{31'h0, _wdata_T_2[22:0]} << wdata_rawIn_normDist_1;
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wire [8:0] _wdata_rawIn_adjustedExp_T_9 =
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(wdata_rawIn_isZeroExpIn_1
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? {4'hF, ~wdata_rawIn_normDist_1}
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: {1'h0, _wdata_T_2[30:23]}) + {7'h20, wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1};
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wire [2:0] _wdata_T_13 =
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wdata_rawIn_isZeroExpIn_1 & ~_wdata_rawIn_out_isNaN_T_2
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? 3'h0
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: _wdata_rawIn_adjustedExp_T_9[8:6];
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wire [60:0] _GEN_0 =
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(&{_wdata_T_4[2:1], _GEN})
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? {&(_wdata_T_10[51:32]),
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_wdata_rawIn_adjustedExp_T_4[7:1],
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_wdata_T_13[2],
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_wdata_T_10[51:32],
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_wdata_T_2[31],
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_wdata_T_13[1],
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_wdata_T_13[0] | (&(_wdata_rawIn_adjustedExp_T_9[8:7]))
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& _wdata_rawIn_out_isNaN_T_2,
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_wdata_rawIn_adjustedExp_T_9[5:0],
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wdata_rawIn_isZeroExpIn_1
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? {_wdata_rawIn_subnormFract_T_2[21:0], 1'h0}
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: _wdata_T_2[22:0]}
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: {_wdata_rawIn_adjustedExp_T_4[8:0], _wdata_T_10};
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wire curOK =
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{_wdata_T_4[2:1], _GEN} != 3'h7 | _GEN_0[60] == (&(_GEN_0[51:32]));
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wire _GEN_1 = load_wb & ~reset;
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wire [2:0] ex_rm = (&(ex_reg_inst[14:12])) ? io_fcsr_rm : ex_reg_inst[14:12];
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wire _dfma_io_in_valid_T = ex_reg_valid & ex_reg_ctrl_fma;
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wire _write_port_busy_T_16 = ex_reg_ctrl_typeTagOut == 2'h0;
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wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode =
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{_regfile_ext_R2_data[52], _regfile_ext_R2_data[30:29]};
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wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 =
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{3'h0, _regfile_ext_R2_data[52], _regfile_ext_R2_data[30:23]} + 12'h700;
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wire [64:0] fpmu_io_in_bits_in1 =
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ex_reg_ctrl_typeTagIn[0] | (&(_regfile_ext_R2_data[64:60]))
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? (ex_reg_ctrl_typeTagIn[0]
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? _regfile_ext_R2_data
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: {_regfile_ext_R2_data[31],
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fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0
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| fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5
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? {_regfile_ext_R2_data[52],
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_regfile_ext_R2_data[30:29],
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_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]}
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: _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2,
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_regfile_ext_R2_data[22:0],
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29'h0})
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: 65'hE008000000000000;
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wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode =
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{_regfile_ext_R1_data[52], _regfile_ext_R1_data[30:29]};
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wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 =
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{3'h0, _regfile_ext_R1_data[52], _regfile_ext_R1_data[30:23]} + 12'h700;
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wire [64:0] fpmu_io_in_bits_in2 =
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ex_reg_ctrl_typeTagIn[0] | (&(_regfile_ext_R1_data[64:60]))
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? (ex_reg_ctrl_typeTagIn[0]
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? _regfile_ext_R1_data
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: {_regfile_ext_R1_data[31],
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fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0
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| fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5
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? {_regfile_ext_R1_data[52],
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_regfile_ext_R1_data[30:29],
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_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]}
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: _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2,
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_regfile_ext_R1_data[22:0],
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29'h0})
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: 65'hE008000000000000;
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reg [4:0] divSqrt_waddr;
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wire _divSqrt_io_inValid_T = mem_ctrl_typeTagOut == 2'h0;
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wire _divSqrt_io_inValid_T_2 = mem_ctrl_typeTagOut == 2'h1;
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reg [2:0] wen;
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reg [4:0] wbInfo_0_rd;
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reg wbInfo_0_typeTag;
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reg [1:0] wbInfo_0_pipeid;
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reg [4:0] wbInfo_1_rd;
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reg wbInfo_1_typeTag;
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reg [1:0] wbInfo_1_pipeid;
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reg [4:0] wbInfo_2_rd;
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reg wbInfo_2_typeTag;
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reg [1:0] wbInfo_2_pipeid;
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reg write_port_busy;
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wire [4:0] waddr = divSqrt_wen ? divSqrt_waddr : wbInfo_0_rd;
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wire [3:0][64:0] _GEN_2 =
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{{_dfma_io_out_bits_data},
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{_sfma_io_out_bits_data},
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{_ifpu_io_out_bits_data},
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{_fpmu_io_out_bits_data}};
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wire [64:0] _wdata_T_29 = divSqrt_wen ? divSqrt_wdata : _GEN_2[wbInfo_0_pipeid];
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wire [64:0] wdata_1 =
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(divSqrt_wen ? divSqrt_typeTag : wbInfo_0_typeTag)
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? _wdata_T_29
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: {12'hFFF, _wdata_T_29[31], 20'hFFFFF, _wdata_T_29[32], _wdata_T_29[30:0]};
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wire [3:0][4:0] _GEN_3 =
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{{_dfma_io_out_bits_exc},
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{_sfma_io_out_bits_exc},
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{_ifpu_io_out_bits_exc},
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{_fpmu_io_out_bits_exc}};
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wire frfWriteBundle_1_wrenf = wen[0] | divSqrt_wen;
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wire curOK_1 = wdata_1[63:61] != 3'h7 | wdata_1[60] == (&(wdata_1[51:32]));
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wire _GEN_4 = frfWriteBundle_1_wrenf & ~reset;
|
|
`ifndef SYNTHESIS
|
|
always @(posedge clock) begin
|
|
if ((`PRINTF_COND_) & _GEN_1 & ~curOK)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at FPU.scala:823 assert(consistent(wdata))\n");
|
|
if ((`PRINTF_COND_) & _GEN_4 & ~curOK_1)
|
|
$fwrite(32'h80000002,
|
|
"Assertion failed\n at FPU.scala:970 assert(consistent(wdata))\n");
|
|
end // always @(posedge)
|
|
`endif // not def SYNTHESIS
|
|
wire wb_toint_valid = wb_reg_valid & wb_ctrl_toint;
|
|
reg [4:0] wb_toint_exc;
|
|
wire _divSqrt_inValid_T = mem_ctrl_div | mem_ctrl_sqrt;
|
|
wire io_nack_mem_0 =
|
|
write_port_busy | _divSqrt_inValid_T & (|wen) | divSqrt_inFlight;
|
|
reg io_sboard_set_REG;
|
|
wire divSqrt_inValid =
|
|
mem_reg_valid & _divSqrt_inValid_T & ~divSqrt_inFlight;
|
|
reg divSqrt_killed;
|
|
wire [8:0] _divSqrt_io_a_expOut_commonCase_T =
|
|
_fpiu_io_out_bits_in_in1[60:52] - 9'h100;
|
|
wire [8:0] _divSqrt_io_b_expOut_commonCase_T =
|
|
_fpiu_io_out_bits_in_in2[60:52] - 9'h100;
|
|
assign divSqrt_typeTag = _divSqrt_1_io_outValid_div | _divSqrt_1_io_outValid_sqrt;
|
|
assign divSqrt_wen =
|
|
divSqrt_typeTag
|
|
? ~divSqrt_killed
|
|
: (_divSqrt_io_outValid_div | _divSqrt_io_outValid_sqrt) & ~divSqrt_killed;
|
|
assign divSqrt_wdata =
|
|
divSqrt_typeTag
|
|
? ({65{_divSqrt_1_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF)
|
|
& _divSqrt_1_io_out
|
|
: {32'h0, _divSqrt_io_out};
|
|
assign divSqrt_flags =
|
|
divSqrt_typeTag ? _divSqrt_1_io_exceptionFlags : _divSqrt_io_exceptionFlags;
|
|
assign divSqrt_inFlight =
|
|
~divSqrt_killed & (~_divSqrt_1_io_inReady | ~_divSqrt_io_inReady);
|
|
always @(posedge clock) begin
|
|
automatic logic [2:0] memLatencyMask;
|
|
automatic logic mem_wen;
|
|
automatic logic [1:0] _GEN_5;
|
|
memLatencyMask =
|
|
{1'h0,
|
|
{1'h0, mem_ctrl_fastpipe | mem_ctrl_fromint}
|
|
| {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}}
|
|
| {mem_ctrl_fma & _divSqrt_io_inValid_T_2, 2'h0};
|
|
mem_wen = mem_reg_valid & (mem_ctrl_fma | mem_ctrl_fastpipe | mem_ctrl_fromint);
|
|
_GEN_5 = {1'h0, mem_ctrl_fromint};
|
|
if (reset) begin
|
|
ex_reg_valid <= 1'h0;
|
|
mem_reg_valid <= 1'h0;
|
|
wb_reg_valid <= 1'h0;
|
|
wen <= 3'h0;
|
|
divSqrt_killed <= 1'h1;
|
|
end
|
|
else begin
|
|
automatic logic _killm_T = io_killm | io_nack_mem_0;
|
|
ex_reg_valid <= io_valid;
|
|
mem_reg_valid <= ex_reg_valid & ~(io_killx | mem_reg_valid & _killm_T);
|
|
wb_reg_valid <= mem_reg_valid & ~_killm_T;
|
|
wen <= {3{mem_wen & ~_killm_T}} & memLatencyMask | {1'h0, wen[2:1]};
|
|
divSqrt_killed <= divSqrt_inValid & _killm_T;
|
|
end
|
|
if (io_valid) begin
|
|
ex_reg_inst <= io_inst;
|
|
ex_reg_ctrl_ren2 <= _fp_decoder_io_sigs_ren2;
|
|
ex_reg_ctrl_ren3 <= _fp_decoder_io_sigs_ren3;
|
|
ex_reg_ctrl_swap23 <= _fp_decoder_io_sigs_swap23;
|
|
ex_reg_ctrl_typeTagIn <= _fp_decoder_io_sigs_typeTagIn;
|
|
ex_reg_ctrl_typeTagOut <= _fp_decoder_io_sigs_typeTagOut;
|
|
ex_reg_ctrl_fromint <= _fp_decoder_io_sigs_fromint;
|
|
ex_reg_ctrl_toint <= _fp_decoder_io_sigs_toint;
|
|
ex_reg_ctrl_fastpipe <= _fp_decoder_io_sigs_fastpipe;
|
|
ex_reg_ctrl_fma <= _fp_decoder_io_sigs_fma;
|
|
ex_reg_ctrl_div <= _fp_decoder_io_sigs_div;
|
|
ex_reg_ctrl_sqrt <= _fp_decoder_io_sigs_sqrt;
|
|
ex_reg_ctrl_wflags <= _fp_decoder_io_sigs_wflags;
|
|
if (_fp_decoder_io_sigs_ren2 & _fp_decoder_io_sigs_swap12)
|
|
ex_ra_0 <= io_inst[24:20];
|
|
else if (_fp_decoder_io_sigs_ren1 & ~_fp_decoder_io_sigs_swap12)
|
|
ex_ra_0 <= io_inst[19:15];
|
|
if (_fp_decoder_io_sigs_ren2 & ~_fp_decoder_io_sigs_swap12
|
|
& ~_fp_decoder_io_sigs_swap23)
|
|
ex_ra_1 <= io_inst[24:20];
|
|
else if (_fp_decoder_io_sigs_ren1 & _fp_decoder_io_sigs_swap12)
|
|
ex_ra_1 <= io_inst[19:15];
|
|
if (_fp_decoder_io_sigs_ren3)
|
|
ex_ra_2 <= io_inst[31:27];
|
|
else if (_fp_decoder_io_sigs_ren2 & _fp_decoder_io_sigs_swap23)
|
|
ex_ra_2 <= io_inst[24:20];
|
|
end
|
|
load_wb <= io_ll_resp_val;
|
|
if (io_ll_resp_val) begin
|
|
load_wb_typeTag <= io_ll_resp_type[1:0] - 2'h2;
|
|
load_wb_data <= io_ll_resp_data;
|
|
load_wb_tag <= io_ll_resp_tag;
|
|
end
|
|
if (ex_reg_valid) begin
|
|
mem_reg_inst <= ex_reg_inst;
|
|
mem_ctrl_typeTagOut <= ex_reg_ctrl_typeTagOut;
|
|
mem_ctrl_fromint <= ex_reg_ctrl_fromint;
|
|
mem_ctrl_toint <= ex_reg_ctrl_toint;
|
|
mem_ctrl_fastpipe <= ex_reg_ctrl_fastpipe;
|
|
mem_ctrl_fma <= ex_reg_ctrl_fma;
|
|
mem_ctrl_div <= ex_reg_ctrl_div;
|
|
mem_ctrl_sqrt <= ex_reg_ctrl_sqrt;
|
|
mem_ctrl_wflags <= ex_reg_ctrl_wflags;
|
|
write_port_busy <=
|
|
|{mem_wen
|
|
& (|(({1'h0, {ex_reg_ctrl_fastpipe, 1'h0} | {ex_reg_ctrl_fromint, 1'h0}}
|
|
| {ex_reg_ctrl_fma & _write_port_busy_T_16, 2'h0}) & memLatencyMask)),
|
|
(ex_reg_ctrl_fastpipe | ex_reg_ctrl_fromint) & wen[2]};
|
|
end
|
|
if (mem_reg_valid)
|
|
wb_ctrl_toint <= mem_ctrl_toint;
|
|
if (divSqrt_inValid)
|
|
divSqrt_waddr <= mem_reg_inst[11:7];
|
|
if (mem_wen & ~write_port_busy & memLatencyMask[0]) begin
|
|
wbInfo_0_rd <= mem_reg_inst[11:7];
|
|
wbInfo_0_typeTag <= mem_ctrl_typeTagOut[0];
|
|
wbInfo_0_pipeid <=
|
|
_GEN_5 | {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}
|
|
| {2{mem_ctrl_fma & _divSqrt_io_inValid_T_2}};
|
|
end
|
|
else if (wen[1]) begin
|
|
wbInfo_0_rd <= wbInfo_1_rd;
|
|
wbInfo_0_typeTag <= wbInfo_1_typeTag;
|
|
wbInfo_0_pipeid <= wbInfo_1_pipeid;
|
|
end
|
|
if (mem_wen & ~write_port_busy & memLatencyMask[1]) begin
|
|
wbInfo_1_rd <= mem_reg_inst[11:7];
|
|
wbInfo_1_typeTag <= mem_ctrl_typeTagOut[0];
|
|
wbInfo_1_pipeid <=
|
|
_GEN_5 | {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}
|
|
| {2{mem_ctrl_fma & _divSqrt_io_inValid_T_2}};
|
|
end
|
|
else if (wen[2]) begin
|
|
wbInfo_1_rd <= wbInfo_2_rd;
|
|
wbInfo_1_typeTag <= wbInfo_2_typeTag;
|
|
wbInfo_1_pipeid <= wbInfo_2_pipeid;
|
|
end
|
|
if (mem_wen & ~write_port_busy & memLatencyMask[2]) begin
|
|
wbInfo_2_rd <= mem_reg_inst[11:7];
|
|
wbInfo_2_typeTag <= mem_ctrl_typeTagOut[0];
|
|
wbInfo_2_pipeid <=
|
|
_GEN_5 | {mem_ctrl_fma & _divSqrt_io_inValid_T, 1'h0}
|
|
| {2{mem_ctrl_fma & _divSqrt_io_inValid_T_2}};
|
|
end
|
|
if (mem_ctrl_toint)
|
|
wb_toint_exc <= _fpiu_io_out_bits_exc;
|
|
io_sboard_set_REG <=
|
|
mem_ctrl_fma & _divSqrt_io_inValid_T_2 | mem_ctrl_div | mem_ctrl_sqrt;
|
|
end // always @(posedge)
|
|
FPUDecoder fp_decoder (
|
|
.io_inst (io_inst),
|
|
.io_sigs_wen (io_dec_wen),
|
|
.io_sigs_ren1 (_fp_decoder_io_sigs_ren1),
|
|
.io_sigs_ren2 (_fp_decoder_io_sigs_ren2),
|
|
.io_sigs_ren3 (_fp_decoder_io_sigs_ren3),
|
|
.io_sigs_swap12 (_fp_decoder_io_sigs_swap12),
|
|
.io_sigs_swap23 (_fp_decoder_io_sigs_swap23),
|
|
.io_sigs_typeTagIn (_fp_decoder_io_sigs_typeTagIn),
|
|
.io_sigs_typeTagOut (_fp_decoder_io_sigs_typeTagOut),
|
|
.io_sigs_fromint (_fp_decoder_io_sigs_fromint),
|
|
.io_sigs_toint (_fp_decoder_io_sigs_toint),
|
|
.io_sigs_fastpipe (_fp_decoder_io_sigs_fastpipe),
|
|
.io_sigs_fma (_fp_decoder_io_sigs_fma),
|
|
.io_sigs_div (_fp_decoder_io_sigs_div),
|
|
.io_sigs_sqrt (_fp_decoder_io_sigs_sqrt),
|
|
.io_sigs_wflags (_fp_decoder_io_sigs_wflags)
|
|
);
|
|
regfile_32x65 regfile_ext (
|
|
.R0_addr (ex_ra_2),
|
|
.R0_en (1'h1),
|
|
.R0_clk (clock),
|
|
.R0_data (_regfile_ext_R0_data),
|
|
.R1_addr (ex_ra_1),
|
|
.R1_en (1'h1),
|
|
.R1_clk (clock),
|
|
.R1_data (_regfile_ext_R1_data),
|
|
.R2_addr (ex_ra_0),
|
|
.R2_en (1'h1),
|
|
.R2_clk (clock),
|
|
.R2_data (_regfile_ext_R2_data),
|
|
.W0_addr (waddr),
|
|
.W0_en (frfWriteBundle_1_wrenf),
|
|
.W0_clk (clock),
|
|
.W0_data (wdata_1),
|
|
.W1_addr (load_wb_tag),
|
|
.W1_en (load_wb),
|
|
.W1_clk (clock),
|
|
.W1_data ({_wdata_T_2[63], _wdata_T_4[2:1], _GEN, _GEN_0})
|
|
);
|
|
FPUFMAPipe_l3_f32 sfma (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_in_valid (_dfma_io_in_valid_T & _write_port_busy_T_16),
|
|
.io_in_bits_ren3 (ex_reg_ctrl_ren3),
|
|
.io_in_bits_swap23 (ex_reg_ctrl_swap23),
|
|
.io_in_bits_rm (ex_rm),
|
|
.io_in_bits_fmaCmd
|
|
({ex_reg_inst[3], ex_reg_inst[2] | ~ex_reg_ctrl_ren3 & ex_reg_inst[27]}),
|
|
.io_in_bits_in1
|
|
({32'h0,
|
|
{_regfile_ext_R2_data[31], _regfile_ext_R2_data[52], _regfile_ext_R2_data[30:0]}
|
|
| ((&(_regfile_ext_R2_data[64:60])) ? 33'h0 : 33'hE0400000)}),
|
|
.io_in_bits_in2
|
|
({32'h0,
|
|
{_regfile_ext_R1_data[31], _regfile_ext_R1_data[52], _regfile_ext_R1_data[30:0]}
|
|
| ((&(_regfile_ext_R1_data[64:60])) ? 33'h0 : 33'hE0400000)}),
|
|
.io_in_bits_in3
|
|
({32'h0,
|
|
{_regfile_ext_R0_data[31], _regfile_ext_R0_data[52], _regfile_ext_R0_data[30:0]}
|
|
| ((&(_regfile_ext_R0_data[64:60])) ? 33'h0 : 33'hE0400000)}),
|
|
.io_out_bits_data (_sfma_io_out_bits_data),
|
|
.io_out_bits_exc (_sfma_io_out_bits_exc)
|
|
);
|
|
FPToInt fpiu (
|
|
.clock (clock),
|
|
.io_in_valid
|
|
(ex_reg_valid
|
|
& (ex_reg_ctrl_toint | ex_reg_ctrl_div | ex_reg_ctrl_sqrt | ex_reg_ctrl_fastpipe
|
|
& ex_reg_ctrl_wflags)),
|
|
.io_in_bits_ren2 (ex_reg_ctrl_ren2),
|
|
.io_in_bits_typeTagOut (ex_reg_ctrl_typeTagOut),
|
|
.io_in_bits_wflags (ex_reg_ctrl_wflags),
|
|
.io_in_bits_rm (ex_rm),
|
|
.io_in_bits_typ (ex_reg_inst[21:20]),
|
|
.io_in_bits_fmt (ex_reg_inst[26:25]),
|
|
.io_in_bits_in1 (fpmu_io_in_bits_in1),
|
|
.io_in_bits_in2 (fpmu_io_in_bits_in2),
|
|
.io_out_bits_in_rm (_fpiu_io_out_bits_in_rm),
|
|
.io_out_bits_in_in1 (_fpiu_io_out_bits_in_in1),
|
|
.io_out_bits_in_in2 (_fpiu_io_out_bits_in_in2),
|
|
.io_out_bits_lt (_fpiu_io_out_bits_lt),
|
|
.io_out_bits_store (io_store_data),
|
|
.io_out_bits_toint (io_toint_data),
|
|
.io_out_bits_exc (_fpiu_io_out_bits_exc)
|
|
);
|
|
IntToFP ifpu (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_in_valid (ex_reg_valid & ex_reg_ctrl_fromint),
|
|
.io_in_bits_typeTagIn (ex_reg_ctrl_typeTagIn),
|
|
.io_in_bits_wflags (ex_reg_ctrl_wflags),
|
|
.io_in_bits_rm (ex_rm),
|
|
.io_in_bits_typ (ex_reg_inst[21:20]),
|
|
.io_in_bits_in1 (io_fromint_data),
|
|
.io_out_bits_data (_ifpu_io_out_bits_data),
|
|
.io_out_bits_exc (_ifpu_io_out_bits_exc)
|
|
);
|
|
FPToFP fpmu (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_in_valid (ex_reg_valid & ex_reg_ctrl_fastpipe),
|
|
.io_in_bits_ren2 (ex_reg_ctrl_ren2),
|
|
.io_in_bits_typeTagOut (ex_reg_ctrl_typeTagOut),
|
|
.io_in_bits_wflags (ex_reg_ctrl_wflags),
|
|
.io_in_bits_rm (ex_rm),
|
|
.io_in_bits_in1 (fpmu_io_in_bits_in1),
|
|
.io_in_bits_in2 (fpmu_io_in_bits_in2),
|
|
.io_out_bits_data (_fpmu_io_out_bits_data),
|
|
.io_out_bits_exc (_fpmu_io_out_bits_exc),
|
|
.io_lt (_fpiu_io_out_bits_lt)
|
|
);
|
|
FPUFMAPipe_l4_f64 dfma (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_in_valid (_dfma_io_in_valid_T & ex_reg_ctrl_typeTagOut == 2'h1),
|
|
.io_in_bits_ren3 (ex_reg_ctrl_ren3),
|
|
.io_in_bits_swap23 (ex_reg_ctrl_swap23),
|
|
.io_in_bits_rm (ex_rm),
|
|
.io_in_bits_fmaCmd
|
|
({ex_reg_inst[3], ex_reg_inst[2] | ~ex_reg_ctrl_ren3 & ex_reg_inst[27]}),
|
|
.io_in_bits_in1 (_regfile_ext_R2_data),
|
|
.io_in_bits_in2 (_regfile_ext_R1_data),
|
|
.io_in_bits_in3 (_regfile_ext_R0_data),
|
|
.io_out_bits_data (_dfma_io_out_bits_data),
|
|
.io_out_bits_exc (_dfma_io_out_bits_exc)
|
|
);
|
|
DivSqrtRecFN_small divSqrt (
|
|
.clock (clock),
|
|
.reset (divSqrt_killed),
|
|
.io_inReady (_divSqrt_io_inReady),
|
|
.io_inValid (divSqrt_inValid & _divSqrt_io_inValid_T),
|
|
.io_sqrtOp (mem_ctrl_sqrt),
|
|
.io_a
|
|
({_fpiu_io_out_bits_in_in1[64],
|
|
_fpiu_io_out_bits_in_in1[63:61] == 3'h0 | _fpiu_io_out_bits_in_in1[63:61] > 3'h5
|
|
? {_fpiu_io_out_bits_in_in1[63:61], _divSqrt_io_a_expOut_commonCase_T[5:0]}
|
|
: _divSqrt_io_a_expOut_commonCase_T,
|
|
_fpiu_io_out_bits_in_in1[51:29]}),
|
|
.io_b
|
|
({_fpiu_io_out_bits_in_in2[64],
|
|
_fpiu_io_out_bits_in_in2[63:61] == 3'h0 | _fpiu_io_out_bits_in_in2[63:61] > 3'h5
|
|
? {_fpiu_io_out_bits_in_in2[63:61], _divSqrt_io_b_expOut_commonCase_T[5:0]}
|
|
: _divSqrt_io_b_expOut_commonCase_T,
|
|
_fpiu_io_out_bits_in_in2[51:29]}),
|
|
.io_roundingMode (_fpiu_io_out_bits_in_rm),
|
|
.io_outValid_div (_divSqrt_io_outValid_div),
|
|
.io_outValid_sqrt (_divSqrt_io_outValid_sqrt),
|
|
.io_out (_divSqrt_io_out),
|
|
.io_exceptionFlags (_divSqrt_io_exceptionFlags)
|
|
);
|
|
DivSqrtRecFN_small_1 divSqrt_1 (
|
|
.clock (clock),
|
|
.reset (divSqrt_killed),
|
|
.io_inReady (_divSqrt_1_io_inReady),
|
|
.io_inValid (divSqrt_inValid & _divSqrt_io_inValid_T_2),
|
|
.io_sqrtOp (mem_ctrl_sqrt),
|
|
.io_a (_fpiu_io_out_bits_in_in1),
|
|
.io_b (_fpiu_io_out_bits_in_in2),
|
|
.io_roundingMode (_fpiu_io_out_bits_in_rm),
|
|
.io_outValid_div (_divSqrt_1_io_outValid_div),
|
|
.io_outValid_sqrt (_divSqrt_1_io_outValid_sqrt),
|
|
.io_out (_divSqrt_1_io_out),
|
|
.io_exceptionFlags (_divSqrt_1_io_exceptionFlags)
|
|
);
|
|
assign io_fcsr_flags_valid = wb_toint_valid | divSqrt_wen | wen[0];
|
|
assign io_fcsr_flags_bits =
|
|
(wb_toint_valid ? wb_toint_exc : 5'h0) | (divSqrt_wen ? divSqrt_flags : 5'h0)
|
|
| (wen[0] ? _GEN_3[wbInfo_0_pipeid] : 5'h0);
|
|
assign io_fcsr_rdy =
|
|
~((|{ex_reg_valid & ex_reg_ctrl_wflags | mem_reg_valid & mem_ctrl_wflags
|
|
| wb_toint_valid,
|
|
wen}) | divSqrt_inFlight);
|
|
assign io_nack_mem = io_nack_mem_0;
|
|
assign io_illegal_rm =
|
|
io_inst[14:12] == 3'h5 | io_inst[14:12] == 3'h6 | (&(io_inst[14:12]))
|
|
& io_fcsr_rm > 3'h4;
|
|
assign io_dec_ren1 = _fp_decoder_io_sigs_ren1;
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assign io_dec_ren2 = _fp_decoder_io_sigs_ren2;
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assign io_dec_ren3 = _fp_decoder_io_sigs_ren3;
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assign io_sboard_set = wb_reg_valid & io_sboard_set_REG;
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assign io_sboard_clr = divSqrt_wen | wen[0] & (&wbInfo_0_pipeid);
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assign io_sboard_clra = waddr;
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endmodule
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