onur
124 lines
4.2 KiB
Systemverilog
124 lines
4.2 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module MulDiv(
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input clock,
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reset,
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output io_req_ready,
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input io_req_valid,
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input [4:0] io_req_bits_fn,
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input io_req_bits_dw,
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input [63:0] io_req_bits_in1,
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io_req_bits_in2,
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input [4:0] io_req_bits_tag,
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input io_kill,
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io_resp_ready,
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output io_resp_valid,
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output [63:0] io_resp_bits_data,
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output [4:0] io_resp_bits_tag
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);
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reg [2:0] state;
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reg req_dw;
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reg [4:0] req_tag;
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reg [6:0] count;
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reg neg_out;
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reg isHi;
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reg resHi;
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reg [64:0] divisor;
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reg [129:0] remainder;
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wire [63:0] result = resHi ? remainder[128:65] : remainder[63:0];
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wire [31:0] loOut = req_dw | state[0] ? result[31:0] : result[63:32];
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wire io_resp_valid_0 = state == 3'h6 | (&state);
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wire io_req_ready_0 = state == 3'h0;
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always @(posedge clock) begin
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automatic logic [2:0] decoded_invInputs = ~(io_req_bits_fn[2:0]);
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automatic logic decoded_andMatrixOutputs_2_2 =
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&{decoded_invInputs[1], decoded_invInputs[2]};
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automatic logic cmdHi;
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automatic logic lhs_sign;
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automatic logic rhs_sign;
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automatic logic [64:0] _subtractor_T_1;
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automatic logic _GEN;
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automatic logic _GEN_0;
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automatic logic _GEN_1;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic _GEN_4;
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automatic logic _GEN_5;
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cmdHi = |{&{io_req_bits_fn[0], decoded_invInputs[2]}, io_req_bits_fn[1]};
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lhs_sign =
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(|{decoded_invInputs[0], decoded_andMatrixOutputs_2_2})
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& (io_req_bits_dw ? io_req_bits_in1[63] : io_req_bits_in1[31]);
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rhs_sign =
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(|{decoded_andMatrixOutputs_2_2, &{decoded_invInputs[0], io_req_bits_fn[2]}})
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& (io_req_bits_dw ? io_req_bits_in2[63] : io_req_bits_in2[31]);
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_subtractor_T_1 = remainder[128:64] - divisor;
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_GEN = state == 3'h1;
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_GEN_0 = state == 3'h5;
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_GEN_1 = state == 3'h2;
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_GEN_2 = _GEN_1 & count == 7'h3F;
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_GEN_3 = state == 3'h3;
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_GEN_4 = count == 7'h40;
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_GEN_5 = io_req_ready_0 & io_req_valid;
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if (reset)
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state <= 3'h0;
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else if (_GEN_5)
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state <= decoded_invInputs[2] ? 3'h2 : {1'h0, ~(lhs_sign | rhs_sign), 1'h1};
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else if (io_resp_ready & io_resp_valid_0 | io_kill)
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state <= 3'h0;
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else if (_GEN_3 & _GEN_4)
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state <= {1'h1, ~neg_out, 1'h1};
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else if (_GEN_2)
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state <= 3'h6;
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else if (_GEN_0)
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state <= 3'h7;
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else if (_GEN)
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state <= 3'h3;
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if (_GEN_5) begin
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req_dw <= io_req_bits_dw;
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req_tag <= io_req_bits_tag;
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count <= {1'h0, decoded_invInputs[2] & ~io_req_bits_dw, 5'h0};
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isHi <= cmdHi;
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divisor <=
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{rhs_sign,
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io_req_bits_dw ? io_req_bits_in2[63:32] : {32{rhs_sign}},
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io_req_bits_in2[31:0]};
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remainder <=
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{66'h0,
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io_req_bits_dw ? io_req_bits_in1[63:32] : {32{lhs_sign}},
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io_req_bits_in1[31:0]};
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end
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else begin
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if (_GEN_3) begin
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count <= count + 7'h1;
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remainder <=
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{1'h0,
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_subtractor_T_1[64] ? remainder[127:64] : _subtractor_T_1[63:0],
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remainder[63:0],
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~(_subtractor_T_1[64])};
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end
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else if (_GEN_1) begin
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automatic logic [65:0] _prod_T_4 =
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{{65{remainder[64]}}, remainder[0]} * {divisor[64], divisor}
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+ {remainder[129], remainder[129:65]};
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count <= count + 7'h1;
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remainder <=
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{_prod_T_4[65:1], count == 7'h3E & neg_out, _prod_T_4[0], remainder[63:1]};
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end
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else if (_GEN_0 | _GEN & remainder[63])
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remainder <= {66'h0, 64'h0 - result};
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if (_GEN & divisor[63])
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divisor <= _subtractor_T_1;
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end
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neg_out <=
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_GEN_5
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? (cmdHi ? lhs_sign : lhs_sign != rhs_sign)
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: ~(_GEN_3 & count == 7'h0 & ~(_subtractor_T_1[64]) & ~isHi) & neg_out;
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resHi <= ~_GEN_5 & (_GEN_3 & _GEN_4 | _GEN_2 ? isHi : ~_GEN_0 & resHi);
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end // always @(posedge)
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assign io_req_ready = io_req_ready_0;
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assign io_resp_valid = io_resp_valid_0;
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assign io_resp_bits_data = {req_dw ? result[63:32] : {32{loOut[31]}}, loOut};
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assign io_resp_bits_tag = req_tag;
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endmodule
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