onur
267 lines
13 KiB
Systemverilog
267 lines
13 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module TLFragmenter_FPGAGPS(
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input clock,
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reset,
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output auto_anon_in_a_ready,
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input auto_anon_in_a_valid,
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input [2:0] auto_anon_in_a_bits_opcode,
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auto_anon_in_a_bits_param,
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auto_anon_in_a_bits_size,
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input [1:0] auto_anon_in_a_bits_source,
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input [28:0] auto_anon_in_a_bits_address,
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input auto_anon_in_a_bits_user_amba_prot_bufferable,
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auto_anon_in_a_bits_user_amba_prot_modifiable,
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auto_anon_in_a_bits_user_amba_prot_readalloc,
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auto_anon_in_a_bits_user_amba_prot_writealloc,
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auto_anon_in_a_bits_user_amba_prot_privileged,
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auto_anon_in_a_bits_user_amba_prot_secure,
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auto_anon_in_a_bits_user_amba_prot_fetch,
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input [3:0] auto_anon_in_a_bits_mask,
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input [31:0] auto_anon_in_a_bits_data,
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input auto_anon_in_a_bits_corrupt,
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auto_anon_in_d_ready,
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output auto_anon_in_d_valid,
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output [2:0] auto_anon_in_d_bits_opcode,
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output [1:0] auto_anon_in_d_bits_param,
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output [2:0] auto_anon_in_d_bits_size,
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output [1:0] auto_anon_in_d_bits_source,
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output auto_anon_in_d_bits_sink,
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auto_anon_in_d_bits_denied,
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output [31:0] auto_anon_in_d_bits_data,
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output auto_anon_in_d_bits_corrupt,
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input auto_anon_out_a_ready,
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output auto_anon_out_a_valid,
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output [2:0] auto_anon_out_a_bits_opcode,
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auto_anon_out_a_bits_param,
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output [1:0] auto_anon_out_a_bits_size,
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output [6:0] auto_anon_out_a_bits_source,
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output [28:0] auto_anon_out_a_bits_address,
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output auto_anon_out_a_bits_user_amba_prot_bufferable,
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auto_anon_out_a_bits_user_amba_prot_modifiable,
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auto_anon_out_a_bits_user_amba_prot_readalloc,
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auto_anon_out_a_bits_user_amba_prot_writealloc,
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auto_anon_out_a_bits_user_amba_prot_privileged,
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auto_anon_out_a_bits_user_amba_prot_secure,
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auto_anon_out_a_bits_user_amba_prot_fetch,
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output [3:0] auto_anon_out_a_bits_mask,
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output [31:0] auto_anon_out_a_bits_data,
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output auto_anon_out_a_bits_corrupt,
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auto_anon_out_d_ready,
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input auto_anon_out_d_valid,
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input [2:0] auto_anon_out_d_bits_opcode,
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input [1:0] auto_anon_out_d_bits_param,
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auto_anon_out_d_bits_size,
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input [6:0] auto_anon_out_d_bits_source,
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input auto_anon_out_d_bits_sink,
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auto_anon_out_d_bits_denied,
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input [31:0] auto_anon_out_d_bits_data,
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input auto_anon_out_d_bits_corrupt
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);
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wire _repeater_io_full;
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wire _repeater_io_deq_valid;
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wire [2:0] _repeater_io_deq_bits_opcode;
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wire [2:0] _repeater_io_deq_bits_size;
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wire [1:0] _repeater_io_deq_bits_source;
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wire [28:0] _repeater_io_deq_bits_address;
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wire [3:0] _repeater_io_deq_bits_mask;
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reg [3:0] acknum;
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reg [2:0] dOrig;
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reg dToggle;
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wire _d_denied_T = |acknum;
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wire [4:0] _dsizeOH1_T = 5'h3 << auto_anon_out_d_bits_size;
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wire [3:0] _GEN = ~(auto_anon_out_d_bits_source[3:0]);
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wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[3:1] & {1'h1, _GEN[3:2]};
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wire [2:0] _dFirst_size_T_8 =
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{1'h0, dFirst_size_hi[2:1]} | {auto_anon_out_d_bits_source[0], ~(_dsizeOH1_T[1:0])}
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& {_GEN[1:0], _dsizeOH1_T[1]};
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wire [2:0] dFirst_size =
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{|dFirst_size_hi,
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|(_dFirst_size_T_8[2:1]),
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_dFirst_size_T_8[2] | _dFirst_size_T_8[0]};
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wire drop =
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~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[3:0]));
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wire anonOut_d_ready = auto_anon_in_d_ready | drop;
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reg r_denied;
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wire d_denied = _d_denied_T & r_denied | auto_anon_out_d_bits_denied;
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wire [1:0] _maxLgHint_T = {_repeater_io_deq_bits_address[15:12] == 4'h0, 1'h0};
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wire [1:0] _maxLgHint_T_1 =
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{{_repeater_io_deq_bits_address[15:13], ~(_repeater_io_deq_bits_address[12])} == 4'h0,
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1'h0};
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wire [1:0] _maxLgHint_T_2 =
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{{_repeater_io_deq_bits_address[15:14],
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_repeater_io_deq_bits_address[13:12] ^ 2'h2} == 4'h0,
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1'h0};
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wire [1:0] _maxLgHint_T_3 =
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{{_repeater_io_deq_bits_address[15:14],
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~(_repeater_io_deq_bits_address[13:12])} == 4'h0,
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1'h0};
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wire [1:0] _maxLgHint_T_4 =
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{{_repeater_io_deq_bits_address[15],
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_repeater_io_deq_bits_address[14:12] ^ 3'h4} == 4'h0,
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1'h0};
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wire [1:0] _maxLgHint_T_5 =
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{{_repeater_io_deq_bits_address[15],
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_repeater_io_deq_bits_address[14:12] ^ 3'h5} == 4'h0,
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1'h0};
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wire [1:0] _maxLgHint_T_6 =
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{{_repeater_io_deq_bits_address[15],
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_repeater_io_deq_bits_address[14:12] ^ 3'h6} == 4'h0,
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1'h0};
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wire [1:0] _maxLgHint_T_7 =
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{{_repeater_io_deq_bits_address[15], ~(_repeater_io_deq_bits_address[14:12])} == 4'h0,
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1'h0};
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wire [1:0] _maxLgHint_T_8 = {_repeater_io_deq_bits_address[15:12] == 4'h8, 1'h0};
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wire [1:0] _maxLgHint_T_9 = {_repeater_io_deq_bits_address[15:12] == 4'h9, 1'h0};
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wire [1:0] _maxLgHint_T_10 = {_repeater_io_deq_bits_address[15:12] == 4'hA, 1'h0};
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wire [7:0][1:0] _GEN_0 =
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{{2'h2},
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{2'h2},
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{_maxLgHint_T | _maxLgHint_T_1 | _maxLgHint_T_2 | _maxLgHint_T_3 | _maxLgHint_T_4
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| _maxLgHint_T_5 | _maxLgHint_T_6 | _maxLgHint_T_7 | _maxLgHint_T_8
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| _maxLgHint_T_9 | _maxLgHint_T_10},
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{_maxLgHint_T | _maxLgHint_T_1 | _maxLgHint_T_2 | _maxLgHint_T_3 | _maxLgHint_T_4
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| _maxLgHint_T_5 | _maxLgHint_T_6 | _maxLgHint_T_7 | _maxLgHint_T_8
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| _maxLgHint_T_9 | _maxLgHint_T_10},
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{_maxLgHint_T | _maxLgHint_T_1 | _maxLgHint_T_2 | _maxLgHint_T_3 | _maxLgHint_T_4
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| _maxLgHint_T_5 | _maxLgHint_T_6 | _maxLgHint_T_7 | _maxLgHint_T_8
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| _maxLgHint_T_9 | _maxLgHint_T_10},
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{_maxLgHint_T | _maxLgHint_T_1 | _maxLgHint_T_2 | _maxLgHint_T_3 | _maxLgHint_T_4
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| _maxLgHint_T_5 | _maxLgHint_T_6 | _maxLgHint_T_7 | _maxLgHint_T_8
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| _maxLgHint_T_9 | _maxLgHint_T_10},
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{_maxLgHint_T | _maxLgHint_T_1 | _maxLgHint_T_2 | _maxLgHint_T_3 | _maxLgHint_T_4
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| _maxLgHint_T_5 | _maxLgHint_T_6 | _maxLgHint_T_7 | _maxLgHint_T_8
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| _maxLgHint_T_9 | _maxLgHint_T_10},
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{_maxLgHint_T | _maxLgHint_T_1 | _maxLgHint_T_2 | _maxLgHint_T_3 | _maxLgHint_T_4
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| _maxLgHint_T_5 | _maxLgHint_T_6 | _maxLgHint_T_7 | _maxLgHint_T_8
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| _maxLgHint_T_9 | _maxLgHint_T_10}};
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wire [1:0] limit = _GEN_0[_repeater_io_deq_bits_opcode];
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wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size;
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reg [3:0] gennum;
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wire aFirst = gennum == 4'h0;
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wire [3:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:2]) : gennum - 4'h1;
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reg aToggle_r;
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wire _GEN_1 = ~_repeater_io_full | _repeater_io_deq_bits_opcode[2];
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wire _GEN_2 = ~_repeater_io_full | (&_repeater_io_deq_bits_mask);
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset & ~_GEN_1)
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$fwrite(32'h80000002,
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"Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n");
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if ((`PRINTF_COND_) & ~reset & ~_GEN_2)
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$fwrite(32'h80000002,
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"Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
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end // always @(posedge)
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`endif // not def SYNTHESIS
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always @(posedge clock) begin
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automatic logic _GEN_3;
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automatic logic _GEN_4;
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_GEN_3 = anonOut_d_ready & auto_anon_out_d_valid;
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_GEN_4 = _GEN_3 & ~_d_denied_T;
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if (~reset) begin
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end
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if (reset) begin
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acknum <= 4'h0;
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dToggle <= 1'h0;
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gennum <= 4'h0;
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end
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else begin
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if (_GEN_3)
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acknum <=
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_d_denied_T
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? acknum
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- {3'h0, auto_anon_out_d_bits_opcode[0] | auto_anon_out_d_bits_size == 2'h2}
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: auto_anon_out_d_bits_source[3:0];
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if (_GEN_4)
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dToggle <= auto_anon_out_d_bits_source[4];
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if (auto_anon_out_a_ready & _repeater_io_deq_valid)
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gennum <= aFragnum;
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end
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if (_GEN_4)
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dOrig <= dFirst_size;
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if (_GEN_3)
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r_denied <= d_denied;
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if (aFirst)
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aToggle_r <= dToggle;
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end // always @(posedge)
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Repeater_TLBundleA_a29d32s2k1z3u repeater (
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.clock (clock),
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.reset (reset),
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.io_repeat
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(_repeater_io_deq_bits_opcode[2] & (|aFragnum)),
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.io_full (_repeater_io_full),
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.io_enq_ready (auto_anon_in_a_ready),
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.io_enq_valid (auto_anon_in_a_valid),
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.io_enq_bits_opcode (auto_anon_in_a_bits_opcode),
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.io_enq_bits_param (auto_anon_in_a_bits_param),
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.io_enq_bits_size (auto_anon_in_a_bits_size),
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.io_enq_bits_source (auto_anon_in_a_bits_source),
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.io_enq_bits_address (auto_anon_in_a_bits_address),
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.io_enq_bits_user_amba_prot_bufferable
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(auto_anon_in_a_bits_user_amba_prot_bufferable),
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.io_enq_bits_user_amba_prot_modifiable
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(auto_anon_in_a_bits_user_amba_prot_modifiable),
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.io_enq_bits_user_amba_prot_readalloc (auto_anon_in_a_bits_user_amba_prot_readalloc),
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.io_enq_bits_user_amba_prot_writealloc
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(auto_anon_in_a_bits_user_amba_prot_writealloc),
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.io_enq_bits_user_amba_prot_privileged
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(auto_anon_in_a_bits_user_amba_prot_privileged),
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.io_enq_bits_user_amba_prot_secure (auto_anon_in_a_bits_user_amba_prot_secure),
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.io_enq_bits_user_amba_prot_fetch (auto_anon_in_a_bits_user_amba_prot_fetch),
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.io_enq_bits_mask (auto_anon_in_a_bits_mask),
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.io_enq_bits_corrupt (auto_anon_in_a_bits_corrupt),
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.io_deq_ready (auto_anon_out_a_ready),
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.io_deq_valid (_repeater_io_deq_valid),
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.io_deq_bits_opcode (_repeater_io_deq_bits_opcode),
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.io_deq_bits_param (auto_anon_out_a_bits_param),
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.io_deq_bits_size (_repeater_io_deq_bits_size),
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.io_deq_bits_source (_repeater_io_deq_bits_source),
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.io_deq_bits_address (_repeater_io_deq_bits_address),
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.io_deq_bits_user_amba_prot_bufferable
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(auto_anon_out_a_bits_user_amba_prot_bufferable),
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.io_deq_bits_user_amba_prot_modifiable
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(auto_anon_out_a_bits_user_amba_prot_modifiable),
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.io_deq_bits_user_amba_prot_readalloc
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(auto_anon_out_a_bits_user_amba_prot_readalloc),
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.io_deq_bits_user_amba_prot_writealloc
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(auto_anon_out_a_bits_user_amba_prot_writealloc),
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.io_deq_bits_user_amba_prot_privileged
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(auto_anon_out_a_bits_user_amba_prot_privileged),
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.io_deq_bits_user_amba_prot_secure (auto_anon_out_a_bits_user_amba_prot_secure),
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.io_deq_bits_user_amba_prot_fetch (auto_anon_out_a_bits_user_amba_prot_fetch),
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.io_deq_bits_mask (_repeater_io_deq_bits_mask),
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.io_deq_bits_corrupt (auto_anon_out_a_bits_corrupt)
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);
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assign auto_anon_in_d_valid = auto_anon_out_d_valid & ~drop;
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assign auto_anon_in_d_bits_opcode = auto_anon_out_d_bits_opcode;
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assign auto_anon_in_d_bits_param = auto_anon_out_d_bits_param;
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assign auto_anon_in_d_bits_size = _d_denied_T ? dOrig : dFirst_size;
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assign auto_anon_in_d_bits_source = auto_anon_out_d_bits_source[6:5];
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assign auto_anon_in_d_bits_sink = auto_anon_out_d_bits_sink;
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assign auto_anon_in_d_bits_denied = d_denied;
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assign auto_anon_in_d_bits_data = auto_anon_out_d_bits_data;
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assign auto_anon_in_d_bits_corrupt = auto_anon_out_d_bits_corrupt;
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assign auto_anon_out_a_valid = _repeater_io_deq_valid;
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assign auto_anon_out_a_bits_opcode = _repeater_io_deq_bits_opcode;
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assign auto_anon_out_a_bits_size =
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_repeater_io_deq_bits_size > {1'h0, limit} ? limit : _repeater_io_deq_bits_size[1:0];
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assign auto_anon_out_a_bits_source =
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{_repeater_io_deq_bits_source, ~(aFirst ? dToggle : aToggle_r), aFragnum};
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assign auto_anon_out_a_bits_address =
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{_repeater_io_deq_bits_address[28:6],
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_repeater_io_deq_bits_address[5:0] | {~(aFragnum | _aOrigOH1_T[5:2]), 2'h0}};
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assign auto_anon_out_a_bits_mask = _repeater_io_full ? 4'hF : auto_anon_in_a_bits_mask;
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assign auto_anon_out_a_bits_data = auto_anon_in_a_bits_data;
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assign auto_anon_out_d_ready = anonOut_d_ready;
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endmodule
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