onur
393 lines
16 KiB
Systemverilog
393 lines
16 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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// Users can define 'PRINTF_COND' to add an extra gate to prints.
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`ifndef PRINTF_COND_
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`ifdef PRINTF_COND
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`define PRINTF_COND_ (`PRINTF_COND)
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`else // PRINTF_COND
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`define PRINTF_COND_ 1
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`endif // PRINTF_COND
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`endif // not def PRINTF_COND_
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module TLPLIC(
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input clock,
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reset,
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auto_int_in_0,
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auto_int_in_1,
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auto_int_in_2,
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auto_int_in_3,
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auto_int_in_4,
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auto_int_in_5,
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auto_int_in_6,
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auto_int_in_7,
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auto_int_in_8,
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auto_int_in_9,
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auto_int_in_10,
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output auto_int_out_0,
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auto_in_a_ready,
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input auto_in_a_valid,
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input [2:0] auto_in_a_bits_opcode,
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input [1:0] auto_in_a_bits_size,
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input [5:0] auto_in_a_bits_source,
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input [27:0] auto_in_a_bits_address,
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input [7:0] auto_in_a_bits_mask,
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input [63:0] auto_in_a_bits_data,
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input auto_in_d_ready,
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output auto_in_d_valid,
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output [2:0] auto_in_d_bits_opcode,
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output [1:0] auto_in_d_bits_size,
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output [5:0] auto_in_d_bits_source,
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output [63:0] auto_in_d_bits_data
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);
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wire out_woready_22;
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wire _out_wofireMux_T;
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wire out_backSel_32;
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wire completer_0;
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wire [3:0] completerDev;
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wire claimer_0;
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wire _out_back_front_q_io_deq_valid;
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wire _out_back_front_q_io_deq_bits_read;
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wire [22:0] _out_back_front_q_io_deq_bits_index;
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wire [63:0] _out_back_front_q_io_deq_bits_data;
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wire [7:0] _out_back_front_q_io_deq_bits_mask;
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wire [3:0] _fanin_io_dev;
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wire [2:0] _fanin_io_max;
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wire _gateways_gateway_10_io_plic_valid;
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wire _gateways_gateway_9_io_plic_valid;
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wire _gateways_gateway_8_io_plic_valid;
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wire _gateways_gateway_7_io_plic_valid;
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wire _gateways_gateway_6_io_plic_valid;
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wire _gateways_gateway_5_io_plic_valid;
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wire _gateways_gateway_4_io_plic_valid;
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wire _gateways_gateway_3_io_plic_valid;
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wire _gateways_gateway_2_io_plic_valid;
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wire _gateways_gateway_1_io_plic_valid;
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wire _gateways_gateway_io_plic_valid;
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reg [2:0] priority_0;
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reg [2:0] priority_1;
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reg [2:0] priority_2;
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reg [2:0] priority_3;
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reg [2:0] priority_4;
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reg [2:0] priority_5;
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reg [2:0] priority_6;
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reg [2:0] priority_7;
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reg [2:0] priority_8;
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reg [2:0] priority_9;
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reg [2:0] priority_10;
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reg [2:0] threshold_0;
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reg pending_0;
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reg pending_1;
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reg pending_2;
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reg pending_3;
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reg pending_4;
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reg pending_5;
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reg pending_6;
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reg pending_7;
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reg pending_8;
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reg pending_9;
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reg pending_10;
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reg [6:0] enables_0_0;
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reg [3:0] enables_0_1;
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reg [3:0] maxDevs_0;
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reg [2:0] intnodeOut_0_REG;
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wire _GEN = claimer_0 & claimer_0 - 1'h1;
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wire _GEN_0 = completer_0 & completer_0 - 1'h1;
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wire [15:0] _completedDevs_T = 16'h1 << completerDev;
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wire [10:0] completedDevs = completer_0 ? _completedDevs_T[11:1] : 11'h0;
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wire _out_T_17 =
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{_out_back_front_q_io_deq_bits_index[22:19],
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_out_back_front_q_io_deq_bits_index[17:11],
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_out_back_front_q_io_deq_bits_index[8:3]} == 17'h0;
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wire [31:0] _out_womask_T_22 =
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{{8{_out_back_front_q_io_deq_bits_mask[7]}},
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{8{_out_back_front_q_io_deq_bits_mask[6]}},
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{8{_out_back_front_q_io_deq_bits_mask[5]}},
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{8{_out_back_front_q_io_deq_bits_mask[4]}}};
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assign claimer_0 =
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_out_wofireMux_T & _out_back_front_q_io_deq_bits_read & out_backSel_32 & _out_T_17
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& (|_out_womask_T_22);
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assign completerDev = _out_back_front_q_io_deq_bits_data[35:32];
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`ifndef SYNTHESIS
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always @(posedge clock) begin
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if ((`PRINTF_COND_) & ~reset & _GEN)
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$fwrite(32'h80000002,
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"Assertion failed\n at Plic.scala:249 assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n");
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if ((`PRINTF_COND_) & ~reset & _GEN_0)
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$fwrite(32'h80000002,
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"Assertion failed\n at Plic.scala:266 assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n");
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end // always @(posedge)
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`endif // not def SYNTHESIS
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wire [11:0] _out_completer_0_T = {enables_0_1, enables_0_0, 1'h0} >> completerDev;
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assign completer_0 = out_woready_22 & (&_out_womask_T_22) & _out_completer_0_T[0];
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wire [5:0] out_oindex =
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{_out_back_front_q_io_deq_bits_index[18],
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_out_back_front_q_io_deq_bits_index[10:9],
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_out_back_front_q_io_deq_bits_index[2:0]};
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wire [63:0] _out_backSel_T =
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64'h1
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<< {58'h0,
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_out_back_front_q_io_deq_bits_index[18],
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_out_back_front_q_io_deq_bits_index[10:9],
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_out_back_front_q_io_deq_bits_index[2:0]};
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assign out_backSel_32 = _out_backSel_T[32];
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assign _out_wofireMux_T = _out_back_front_q_io_deq_valid & auto_in_d_ready;
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wire _out_wofireMux_T_2 = _out_wofireMux_T & ~_out_back_front_q_io_deq_bits_read;
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wire out_woready_3 = _out_wofireMux_T_2 & _out_backSel_T[1] & _out_T_17;
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wire out_woready_17 = _out_wofireMux_T_2 & _out_backSel_T[2] & _out_T_17;
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wire out_woready_19 = _out_wofireMux_T_2 & _out_backSel_T[3] & _out_T_17;
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wire out_woready_24 = _out_wofireMux_T_2 & _out_backSel_T[4] & _out_T_17;
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wire out_woready_1 = _out_wofireMux_T_2 & _out_backSel_T[5] & _out_T_17;
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wire out_woready_27 = _out_wofireMux_T_2 & _out_backSel_T[16] & _out_T_17;
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assign out_woready_22 = _out_wofireMux_T_2 & out_backSel_32 & _out_T_17;
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wire _out_out_bits_data_T_9 = out_oindex == 6'h0;
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always @(posedge clock) begin
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if (~reset) begin
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end
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if (_out_wofireMux_T_2 & _out_backSel_T[0] & _out_T_17
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& _out_back_front_q_io_deq_bits_mask[4])
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priority_0 <= _out_back_front_q_io_deq_bits_data[34:32];
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if (out_woready_3 & _out_back_front_q_io_deq_bits_mask[0])
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priority_1 <= _out_back_front_q_io_deq_bits_data[2:0];
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if (out_woready_3 & _out_back_front_q_io_deq_bits_mask[4])
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priority_2 <= _out_back_front_q_io_deq_bits_data[34:32];
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if (out_woready_17 & _out_back_front_q_io_deq_bits_mask[0])
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priority_3 <= _out_back_front_q_io_deq_bits_data[2:0];
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if (out_woready_17 & _out_back_front_q_io_deq_bits_mask[4])
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priority_4 <= _out_back_front_q_io_deq_bits_data[34:32];
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if (out_woready_19 & _out_back_front_q_io_deq_bits_mask[0])
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priority_5 <= _out_back_front_q_io_deq_bits_data[2:0];
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if (out_woready_19 & _out_back_front_q_io_deq_bits_mask[4])
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priority_6 <= _out_back_front_q_io_deq_bits_data[34:32];
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if (out_woready_24 & _out_back_front_q_io_deq_bits_mask[0])
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priority_7 <= _out_back_front_q_io_deq_bits_data[2:0];
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if (out_woready_24 & _out_back_front_q_io_deq_bits_mask[4])
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priority_8 <= _out_back_front_q_io_deq_bits_data[34:32];
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if (out_woready_1 & _out_back_front_q_io_deq_bits_mask[0])
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priority_9 <= _out_back_front_q_io_deq_bits_data[2:0];
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if (out_woready_1 & _out_back_front_q_io_deq_bits_mask[4])
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priority_10 <= _out_back_front_q_io_deq_bits_data[34:32];
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if (out_woready_22 & _out_back_front_q_io_deq_bits_mask[0])
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threshold_0 <= _out_back_front_q_io_deq_bits_data[2:0];
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if (out_woready_27 & _out_back_front_q_io_deq_bits_mask[0])
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enables_0_0 <= _out_back_front_q_io_deq_bits_data[7:1];
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if (out_woready_27 & _out_back_front_q_io_deq_bits_mask[1])
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enables_0_1 <= _out_back_front_q_io_deq_bits_data[11:8];
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maxDevs_0 <= _fanin_io_dev;
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intnodeOut_0_REG <= _fanin_io_max;
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if (reset) begin
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pending_0 <= 1'h0;
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pending_1 <= 1'h0;
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pending_2 <= 1'h0;
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pending_3 <= 1'h0;
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pending_4 <= 1'h0;
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pending_5 <= 1'h0;
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pending_6 <= 1'h0;
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pending_7 <= 1'h0;
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pending_8 <= 1'h0;
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pending_9 <= 1'h0;
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pending_10 <= 1'h0;
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end
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else begin
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automatic logic [15:0] _claimedDevs_T = 16'h1 << (claimer_0 ? maxDevs_0 : 4'h0);
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if (_claimedDevs_T[1] | _gateways_gateway_io_plic_valid)
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pending_0 <= ~(_claimedDevs_T[1]);
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if (_claimedDevs_T[2] | _gateways_gateway_1_io_plic_valid)
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pending_1 <= ~(_claimedDevs_T[2]);
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if (_claimedDevs_T[3] | _gateways_gateway_2_io_plic_valid)
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pending_2 <= ~(_claimedDevs_T[3]);
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if (_claimedDevs_T[4] | _gateways_gateway_3_io_plic_valid)
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pending_3 <= ~(_claimedDevs_T[4]);
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if (_claimedDevs_T[5] | _gateways_gateway_4_io_plic_valid)
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pending_4 <= ~(_claimedDevs_T[5]);
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if (_claimedDevs_T[6] | _gateways_gateway_5_io_plic_valid)
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pending_5 <= ~(_claimedDevs_T[6]);
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if (_claimedDevs_T[7] | _gateways_gateway_6_io_plic_valid)
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pending_6 <= ~(_claimedDevs_T[7]);
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if (_claimedDevs_T[8] | _gateways_gateway_7_io_plic_valid)
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pending_7 <= ~(_claimedDevs_T[8]);
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if (_claimedDevs_T[9] | _gateways_gateway_8_io_plic_valid)
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pending_8 <= ~(_claimedDevs_T[9]);
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if (_claimedDevs_T[10] | _gateways_gateway_9_io_plic_valid)
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pending_9 <= ~(_claimedDevs_T[10]);
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if (_claimedDevs_T[11] | _gateways_gateway_10_io_plic_valid)
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pending_10 <= ~(_claimedDevs_T[11]);
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end
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end // always @(posedge)
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LevelGateway gateways_gateway (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_0),
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.io_plic_valid (_gateways_gateway_io_plic_valid),
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.io_plic_ready (~pending_0),
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.io_plic_complete (completedDevs[0])
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);
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LevelGateway gateways_gateway_1 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_1),
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.io_plic_valid (_gateways_gateway_1_io_plic_valid),
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.io_plic_ready (~pending_1),
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.io_plic_complete (completedDevs[1])
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);
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LevelGateway gateways_gateway_2 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_2),
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.io_plic_valid (_gateways_gateway_2_io_plic_valid),
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.io_plic_ready (~pending_2),
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.io_plic_complete (completedDevs[2])
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);
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LevelGateway gateways_gateway_3 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_3),
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.io_plic_valid (_gateways_gateway_3_io_plic_valid),
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.io_plic_ready (~pending_3),
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.io_plic_complete (completedDevs[3])
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);
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LevelGateway gateways_gateway_4 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_4),
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.io_plic_valid (_gateways_gateway_4_io_plic_valid),
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.io_plic_ready (~pending_4),
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.io_plic_complete (completedDevs[4])
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);
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LevelGateway gateways_gateway_5 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_5),
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.io_plic_valid (_gateways_gateway_5_io_plic_valid),
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.io_plic_ready (~pending_5),
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.io_plic_complete (completedDevs[5])
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);
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LevelGateway gateways_gateway_6 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_6),
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.io_plic_valid (_gateways_gateway_6_io_plic_valid),
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.io_plic_ready (~pending_6),
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.io_plic_complete (completedDevs[6])
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);
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LevelGateway gateways_gateway_7 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_7),
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.io_plic_valid (_gateways_gateway_7_io_plic_valid),
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.io_plic_ready (~pending_7),
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.io_plic_complete (completedDevs[7])
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);
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LevelGateway gateways_gateway_8 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_8),
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.io_plic_valid (_gateways_gateway_8_io_plic_valid),
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.io_plic_ready (~pending_8),
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.io_plic_complete (completedDevs[8])
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);
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LevelGateway gateways_gateway_9 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_9),
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.io_plic_valid (_gateways_gateway_9_io_plic_valid),
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.io_plic_ready (~pending_9),
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.io_plic_complete (completedDevs[9])
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);
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LevelGateway gateways_gateway_10 (
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.clock (clock),
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.reset (reset),
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.io_interrupt (auto_int_in_10),
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.io_plic_valid (_gateways_gateway_10_io_plic_valid),
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.io_plic_ready (~pending_10),
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.io_plic_complete (completedDevs[10])
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);
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PLICFanIn fanin (
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.io_prio_0 (priority_0),
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.io_prio_1 (priority_1),
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.io_prio_2 (priority_2),
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.io_prio_3 (priority_3),
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.io_prio_4 (priority_4),
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.io_prio_5 (priority_5),
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.io_prio_6 (priority_6),
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.io_prio_7 (priority_7),
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.io_prio_8 (priority_8),
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.io_prio_9 (priority_9),
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.io_prio_10 (priority_10),
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.io_ip
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({enables_0_1, enables_0_0}
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& {pending_10,
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pending_9,
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pending_8,
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pending_7,
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pending_6,
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pending_5,
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pending_4,
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pending_3,
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pending_2,
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pending_1,
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pending_0}),
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.io_dev (_fanin_io_dev),
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.io_max (_fanin_io_max)
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);
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Queue1_RegMapperInput_i23_m8 out_back_front_q (
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.clock (clock),
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.reset (reset),
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.io_enq_ready (auto_in_a_ready),
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.io_enq_valid (auto_in_a_valid),
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.io_enq_bits_read (auto_in_a_bits_opcode == 3'h4),
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.io_enq_bits_index (auto_in_a_bits_address[25:3]),
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.io_enq_bits_data (auto_in_a_bits_data),
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.io_enq_bits_mask (auto_in_a_bits_mask),
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.io_enq_bits_extra_tlrr_extra_source (auto_in_a_bits_source),
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.io_enq_bits_extra_tlrr_extra_size (auto_in_a_bits_size),
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.io_deq_ready (auto_in_d_ready),
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.io_deq_valid (_out_back_front_q_io_deq_valid),
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.io_deq_bits_read (_out_back_front_q_io_deq_bits_read),
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.io_deq_bits_index (_out_back_front_q_io_deq_bits_index),
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.io_deq_bits_data (_out_back_front_q_io_deq_bits_data),
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.io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask),
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.io_deq_bits_extra_tlrr_extra_source (auto_in_d_bits_source),
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.io_deq_bits_extra_tlrr_extra_size (auto_in_d_bits_size)
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);
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assign auto_int_out_0 = intnodeOut_0_REG > threshold_0;
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assign auto_in_d_valid = _out_back_front_q_io_deq_valid;
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assign auto_in_d_bits_opcode = {2'h0, _out_back_front_q_io_deq_bits_read};
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assign auto_in_d_bits_data =
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~(_out_out_bits_data_T_9 | out_oindex == 6'h1 | out_oindex == 6'h2
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| out_oindex == 6'h3 | out_oindex == 6'h4 | out_oindex == 6'h5 | out_oindex == 6'h8
|
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| out_oindex == 6'h10 | out_oindex == 6'h20) | _out_T_17
|
|
? (_out_out_bits_data_T_9
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|
? {29'h0, priority_0, 32'h0}
|
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: out_oindex == 6'h1
|
|
? {29'h0, priority_2, 29'h0, priority_1}
|
|
: out_oindex == 6'h2
|
|
? {29'h0, priority_4, 29'h0, priority_3}
|
|
: out_oindex == 6'h3
|
|
? {29'h0, priority_6, 29'h0, priority_5}
|
|
: out_oindex == 6'h4
|
|
? {29'h0, priority_8, 29'h0, priority_7}
|
|
: out_oindex == 6'h5
|
|
? {29'h0, priority_10, 29'h0, priority_9}
|
|
: out_oindex == 6'h8
|
|
? {52'h0,
|
|
pending_10,
|
|
pending_9,
|
|
pending_8,
|
|
pending_7,
|
|
pending_6,
|
|
pending_5,
|
|
pending_4,
|
|
pending_3,
|
|
pending_2,
|
|
pending_1,
|
|
pending_0,
|
|
1'h0}
|
|
: out_oindex == 6'h10
|
|
? {52'h0, enables_0_1, enables_0_0, 1'h0}
|
|
: out_oindex == 6'h20
|
|
? {28'h0, maxDevs_0, 29'h0, threshold_0}
|
|
: 64'h0)
|
|
: 64'h0;
|
|
endmodule
|
|
|