onur
223 lines
7.6 KiB
Markdown
223 lines
7.6 KiB
Markdown
# VCU118 Rocket FPGA Flow
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Bu dizin VCU118 uzerinde Rocket SoC uretmek, bitstream almak ve kart flash'ina
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bitstream/app image yazmak icin sade bir make agaci saglar.
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## Dizinler
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```text
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soc/
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Makefile # ortak SoC girisi
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software/ # bootloader, BSP ve bare-metal uygulamalar
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out/ # ortak ELF, BootROM ve app flash imajlari
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hardware/
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upstream/rocket-chip/ # upstream Rocket Scala/resources symlink gorunumu
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soc/scala/ # proje Scala/Chisel Rocket SoC katmani
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generated/ # FIRRTL ve split SystemVerilog dump alani
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fpga/vcu118/rtl/ # FPGA shell yardimci RTL
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fpga/vcu118/constraints/ # VCU118 XDC
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sim/fpga/vcu118/ # FPGA smoke/sim girisi
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external/gps/rtl/ # GPS RTL kaynaklari ve filelist
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targets/fpga/vcu118/
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Makefile # VCU118 FPGA akisi giris noktasi
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docs/ # detayli HTML dokuman
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flow/vivado/ # Vivado non-project Make/Tcl akisi
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tools/ # VCU118 wrapper generator
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out/ # uretilen tum FPGA ciktilari
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bitstream/
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build/
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flash/
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logs/
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reports/
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```
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## Ana Komutlar
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Her katman kendi klasorunden de calistirilabilir:
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```bash
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make -C soc hw
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make -C soc/software all
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make -C hardware/soc firrtl
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make -C hardware/fpga/vcu118/rtl generated
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make -C targets/fpga/vcu118/flow/vivado bitstream
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make -C targets/fpga/vcu118/flow/vivado flash-app
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make -C hardware/sim/fpga/vcu118 smoke
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```
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Kok Makefile ayni hedefleri tek yerden de sunar:
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```bash
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make -C targets/fpga/vcu118 software
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make -C targets/fpga/vcu118 chisel
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make -C targets/fpga/vcu118 rtl
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make -C targets/fpga/vcu118 soc
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make -C targets/fpga/vcu118 bitstream
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make -C targets/fpga/vcu118 program-fpga
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make -C targets/fpga/vcu118 program-flash
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make -C targets/fpga/vcu118 program-flash-bitstream
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make -C targets/fpga/vcu118 program-flash-combined
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make -C targets/fpga/vcu118 prune
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```
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Gundelik uygulama gelistirme icin:
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```bash
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make -C targets/fpga/vcu118 program-flash
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make -C targets/fpga/vcu118 program-fpga
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```
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Bitstream SRAM'e atildiktan sonra GDB ile RAM'e uygulama yuklemek icin:
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```bash
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make -C targets/fpga/vcu118 debug-openocd
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make -C targets/fpga/vcu118 uart-listen UART_PORT=/dev/ttyUSB2
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make -C targets/fpga/vcu118 debug-load APP=hello_uart
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make -C targets/fpga/vcu118 debug-load APP=gps_system
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```
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Bu akista OpenOCD, Xilinx BSCAN uzerinden Rocket DMI portuna gider. FPGA
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bitstream'inde `rocket_bscan_dmi_tunnel.sv` bulunmalidir.
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## RF girisi
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SoC/fabric saati kartin 300 MHz kristalinden uretilmeye devam eder. GPS
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acquisition ve tracking/PPS saatleri secili RF sample clock'tan beslenen iki
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MMCM kademesinden uretilir. Varsayilan 16.367981 MHz RF referansi once
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55.555556 MHz'e, ardindan 100 MHz acquisition ve 125 MHz tracking saatine
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cevrilir; nominal tracking oran hatasi yaklasik 0.007 ppm'dir. Reset ancak
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fabric ve iki GPS MMCM lock olduktan sonra kalkar.
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RF, acquisition ve tracking domainleri ortak frekans referansina ragmen CDC
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sinirlaridir. Vivado timing scripti bunlari ayri asynchronous gruplar olarak
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tutar; bu ayar RF-referansli frekans coherency'sini degil, mevcut CDC
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protokolunun analiz modelini ifade eder.
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VCU118 FPGA top'u `tools/gen_vcu118_wrapper.py` ile uretilir. RF kaynagi
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`RF_INPUT_MODE` ile secilir:
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```text
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pmod Varsayilan. Harici RF clock + 4-bit RF data PMOD0/J52'den SoC GPS RF portuna gider ve GPS PLL'lerini referanslar.
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generated Dahili RF clock uretilir, RF data 4'd0 olur.
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ethernet Eski raw-Ethernet RF streamer path'i ve PCS/PMA IP aktif olur.
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```
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Varsayilan PMOD akisi:
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```bash
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make -C targets/fpga/vcu118 bitstream
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```
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Eski Ethernet RF akisi sadece `RF_INPUT_MODE=ethernet` bitstream ile kullanilir:
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```bash
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make -C targets/fpga/vcu118 bitstream RF_INPUT_MODE=ethernet
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sudo make -C targets/fpga/vcu118 eth-rf-send
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```
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`pmod` ve `generated` modlarinda Vivado flow Ethernet PCS/PMA IP'yi uretmez,
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`hardware/fpga/vcu118/rtl/ethernet_rf` altindaki RTL'i okumaz ve top-level
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Ethernet PHY portlarini olusturmaz.
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PMOD0/J52 connector tarafi 3.3 V'tur. FPGA U1 tarafinda U41 level shifter
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nedeniyle pinler 1.8 V bankta `LVCMOS18` olarak constrain edilir:
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```text
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port FPGA pin PMOD pin FPGA I/O PMOD header level
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rf_clk_pmod AY14 PMOD0_0 J52.1 LVCMOS18 3.3 V
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rf_data_pmod[0] AY15 PMOD0_1 J52.3 LVCMOS18 3.3 V
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rf_data_pmod[1] AW15 PMOD0_2 J52.5 LVCMOS18 3.3 V
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rf_data_pmod[2] AV15 PMOD0_3 J52.7 LVCMOS18 3.3 V
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rf_data_pmod[3] AV16 PMOD0_4 J52.2 LVCMOS18 3.3 V
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```
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Disaridan sinyal baglarken 3.3 V seviyeyi J52 PMOD header tarafina ver. FPGA
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U1 package pinlerine dogrudan 3.3 V uygulanmaz; o tarafta level shifter sonrasi
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`LVCMOS18` vardir.
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PMOD pin constraintleri `hardware/fpga/vcu118/constraints/vcu118_pmod_rf.xdc`
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dosyasindadir ve sadece `RF_INPUT_MODE=pmod` iken okunur. Ethernet PHY pinleri
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ise `hardware/fpga/vcu118/constraints/vcu118_ethernet.xdc` altindadir ve sadece
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`RF_INPUT_MODE=ethernet` iken okunur.
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PMOD SPI portu her RF modunda aktiftir. SoC register adresi `0x10015000`'dir;
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kart konfig flash'ina bagli mevcut SPI `0x10014000` adresinde kalir.
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SPI, RF icin kullanilan PMOD0/J52 yerine PMOD1/J53'e atanir. Driver
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single/quad calisma modunu secer; single modda sadece `dq[0]` MOSI ve `dq[1]`
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MISO kullanilir.
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```text
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port FPGA pin PMOD pin
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pmod_spi_csn N28 PMOD1_0 J53.1
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pmod_spi_dq[0] M30 PMOD1_1 J53.3 MOSI
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pmod_spi_dq[1] N30 PMOD1_2 J53.5 MISO
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pmod_spi_sck P30 PMOD1_3 J53.7 SCK
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pmod_spi_dq[2] P29 PMOD1_4 J53.2
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pmod_spi_dq[3] L31 PMOD1_5 J53.4
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```
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J53 connector tarafi 3.3 V'tur; FPGA U1 tarafinda U42 level shifter sonrasi
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`LVCMOS12` kullanilir. Pin constraintleri
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`hardware/fpga/vcu118/constraints/vcu118_pmod_spi.xdc` dosyasindadir ve Vivado
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akisi tarafindan her RF modunda okunur.
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MAX2771 icin generic PMOD SPI'dan bagimsiz, 48-clock/tek-SDATA hatli bir IP
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`0x10016000` adresindedir. PMOD0/J52'nin GPS RF tarafindan kullanilmayan son uc
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hatti secilmistir. Bu hatlar U41 uzerinden connector tarafinda 3.3 V seviyesine
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cevrilir. 100 MHz VCU118 fabric saatinden 13 fabric cycle yarim periyot ile
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3.846 MHz SCLK uretilir.
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```text
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port FPGA pin PMOD pin yon
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max2771_spi_sclk AU16 PMOD0_5 J52.4 output
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max2771_spi_csn AT15 PMOD0_6 J52.6 output
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max2771_spi_sdata AT16 PMOD0_7 J52.8 bidirectional
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```
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Constraintler `hardware/fpga/vcu118/constraints/vcu118_max2771_spi.xdc`
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dosyasindadir. Ayni test uygulamasi hardware'in raporladigi board clock ve
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SCLK degerlerini kontrol eder:
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```bash
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make -C targets/fpga/vcu118 debug-load APP=max2771_spi_test
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```
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EV kit uzerindeki MAX32625 PICO ayni uc SPI hattina baglidir. FPGA master
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baglanirken PICO pinleri high-Z olmali veya PICO fiziksel olarak ayrilmali;
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iki master ayni anda surulmemelidir.
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Sensorden gelen external interrupt hatti SPI'dan bagimsizdir. `pmod_irq`
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olarak PMOD1_6/J53.6'ya cikar ve PLIC'te `BSP_PMOD_IRQ` (`11`) ID'siyle
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gorunur.
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```text
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port FPGA pin PMOD pin
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pmod_irq M31 PMOD1_6 J53.6
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```
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Pin constraintleri `hardware/fpga/vcu118/constraints/vcu118_pmod_irq.xdc`
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dosyasindadir ve Vivado akisi tarafindan her RF modunda okunur.
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`fpga-config` ve `help` ciktisi aktif `RF_INPUT_MODE` degerini gosterir.
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Bitstream flash'a kalici yazilacaksa, uzun suren tek seferlik hedef:
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```bash
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make -C targets/fpga/vcu118 program-flash-bitstream
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```
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Gereksiz buyuk ara ciktilari temizlemek, ama mevcut bitstream/app ciktilarini
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korumak icin:
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```bash
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make -C targets/fpga/vcu118 prune
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```
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Detayli aciklama:
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```text
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targets/fpga/vcu118/docs/vcu118_rocket_flash_boot_guide.html
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```
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