onur
93 lines
3.2 KiB
Systemverilog
93 lines
3.2 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module FPToFP(
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input clock,
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reset,
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io_in_valid,
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io_in_bits_ren2,
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input [1:0] io_in_bits_typeTagOut,
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input io_in_bits_wflags,
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input [2:0] io_in_bits_rm,
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input [64:0] io_in_bits_in1,
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io_in_bits_in2,
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output [64:0] io_out_bits_data,
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output [4:0] io_out_bits_exc,
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input io_lt
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);
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wire [32:0] _narrower_io_out;
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wire [4:0] _narrower_io_exceptionFlags;
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reg in_pipe_v;
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reg in_pipe_b_ren2;
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reg [1:0] in_pipe_b_typeTagOut;
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reg in_pipe_b_wflags;
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reg [2:0] in_pipe_b_rm;
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reg [64:0] in_pipe_b_in1;
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reg [64:0] in_pipe_b_in2;
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wire isnan1 = &(in_pipe_b_in1[63:61]);
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wire isnan2 = &(in_pipe_b_in2[63:61]);
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wire _GEN = in_pipe_b_wflags & ~in_pipe_b_ren2;
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wire [64:0] fsgnjMux_data =
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_GEN
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? ((&(in_pipe_b_in1[63:61])) ? 65'hE008000000000000 : in_pipe_b_in1)
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: in_pipe_b_wflags
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? (isnan1 & isnan2
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? 65'hE008000000000000
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: isnan2 | in_pipe_b_rm[0] != io_lt & ~isnan1
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? in_pipe_b_in1
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: in_pipe_b_in2)
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: {in_pipe_b_rm[1]
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? in_pipe_b_in1[64] ^ in_pipe_b_in2[64]
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: in_pipe_b_rm[0] ^ in_pipe_b_in2[64],
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in_pipe_b_in1[63:0]};
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reg [64:0] io_out_pipe_b_data;
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reg [4:0] io_out_pipe_b_exc;
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always @(posedge clock) begin
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if (reset)
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in_pipe_v <= 1'h0;
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else
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in_pipe_v <= io_in_valid;
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if (io_in_valid) begin
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in_pipe_b_ren2 <= io_in_bits_ren2;
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in_pipe_b_typeTagOut <= io_in_bits_typeTagOut;
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in_pipe_b_wflags <= io_in_bits_wflags;
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in_pipe_b_rm <= io_in_bits_rm;
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in_pipe_b_in1 <= io_in_bits_in1;
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in_pipe_b_in2 <= io_in_bits_in2;
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end
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if (in_pipe_v) begin
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automatic logic _GEN_0 = in_pipe_b_typeTagOut == 2'h0;
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automatic logic [8:0] _mux_data_expOut_commonCase_T = fsgnjMux_data[60:52] - 9'h100;
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io_out_pipe_b_data <=
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_GEN_0
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? (_GEN
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? {fsgnjMux_data[64:33], _narrower_io_out}
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: {fsgnjMux_data[64:33],
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fsgnjMux_data[64],
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fsgnjMux_data[63:61] == 3'h0 | fsgnjMux_data[63:61] > 3'h5
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? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T[5:0]}
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: _mux_data_expOut_commonCase_T,
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fsgnjMux_data[51:29]})
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: fsgnjMux_data;
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io_out_pipe_b_exc <=
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_GEN & _GEN_0
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? _narrower_io_exceptionFlags
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: _GEN
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? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]), 4'h0}
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: in_pipe_b_wflags
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? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51])
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| (&(in_pipe_b_in2[63:61])) & ~(in_pipe_b_in2[51]),
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4'h0}
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: 5'h0;
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end
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end // always @(posedge)
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RecFNToRecFN narrower (
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.io_in (in_pipe_b_in1),
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.io_roundingMode (in_pipe_b_rm),
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.io_out (_narrower_io_out),
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.io_exceptionFlags (_narrower_io_exceptionFlags)
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);
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assign io_out_bits_data = io_out_pipe_b_data;
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assign io_out_bits_exc = io_out_pipe_b_exc;
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endmodule
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