onur
107 lines
4.3 KiB
Systemverilog
107 lines
4.3 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module MulAddRecFNToRaw_preMul_1(
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input [1:0] io_op,
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input [64:0] io_a,
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io_b,
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io_c,
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output [52:0] io_mulAddA,
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io_mulAddB,
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output [105:0] io_mulAddC,
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output io_toPostMul_isSigNaNAny,
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io_toPostMul_isNaNAOrB,
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io_toPostMul_isInfA,
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io_toPostMul_isZeroA,
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io_toPostMul_isInfB,
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io_toPostMul_isZeroB,
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io_toPostMul_signProd,
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io_toPostMul_isNaNC,
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io_toPostMul_isInfC,
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io_toPostMul_isZeroC,
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output [12:0] io_toPostMul_sExpSum,
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output io_toPostMul_doSubMags,
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io_toPostMul_CIsDominant,
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output [5:0] io_toPostMul_CDom_CAlignDist,
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output [54:0] io_toPostMul_highAlignedSigC,
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output io_toPostMul_bit0AlignedSigC
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);
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wire _rawA_out_sig_T = |(io_a[63:61]);
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wire rawA_isSpecial = &(io_a[63:62]);
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wire rawA_isNaN = rawA_isSpecial & io_a[61];
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wire _rawB_out_sig_T = |(io_b[63:61]);
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wire rawB_isSpecial = &(io_b[63:62]);
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wire rawB_isNaN = rawB_isSpecial & io_b[61];
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wire _rawC_out_sig_T = |(io_c[63:61]);
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wire rawC_isSpecial = &(io_c[63:62]);
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wire rawC_isNaN = rawC_isSpecial & io_c[61];
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wire signProd = io_a[64] ^ io_b[64] ^ io_op[1];
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wire [13:0] _sExpAlignedProd_T_1 = {2'h0, io_a[63:52]} + {2'h0, io_b[63:52]} - 14'h7C8;
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wire doSubMags = signProd ^ io_c[64] ^ io_op[0];
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wire [13:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[63:52]};
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wire isMinCAlign =
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~_rawA_out_sig_T | ~_rawB_out_sig_T | $signed(_sNatCAlignDist_T) < 14'sh0;
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wire CIsDominant =
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_rawC_out_sig_T & (isMinCAlign | _sNatCAlignDist_T[12:0] < 13'h36);
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wire [7:0] CAlignDist =
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isMinCAlign
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? 8'h0
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: _sNatCAlignDist_T[12:0] < 13'hA1 ? _sNatCAlignDist_T[7:0] : 8'hA1;
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wire [164:0] mainAlignedSigC =
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$unsigned($signed($signed({doSubMags
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? {1'h1, ~_rawC_out_sig_T, ~(io_c[51:0])}
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: {1'h0, _rawC_out_sig_T, io_c[51:0]},
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{111{doSubMags}}}) >>> CAlignDist));
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wire [64:0] reduced4CExtra_shift =
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$unsigned($signed(65'sh10000000000000000 >>> CAlignDist[7:2]));
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wire [7:0] _reduced4CExtra_T_13 =
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{4'h0, reduced4CExtra_shift[31:28]} | {reduced4CExtra_shift[27:24], 4'h0};
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wire [7:0] _reduced4CExtra_T_23 =
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{2'h0, _reduced4CExtra_T_13[7:2] & 6'h33} | {_reduced4CExtra_T_13[5:0] & 6'h33, 2'h0};
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wire [12:0] _GEN =
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{|(io_c[51:48]),
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|(io_c[47:44]),
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|(io_c[43:40]),
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|(io_c[39:36]),
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|(io_c[35:32]),
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|(io_c[31:28]),
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|(io_c[27:24]),
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|(io_c[23:20]),
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|(io_c[19:16]),
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|(io_c[15:12]),
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|(io_c[11:8]),
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|(io_c[7:4]),
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|(io_c[3:0])}
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& {{1'h0, _reduced4CExtra_T_23[7:1] & 7'h55}
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| {_reduced4CExtra_T_23[6:0] & 7'h55, 1'h0},
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reduced4CExtra_shift[32],
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reduced4CExtra_shift[33],
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reduced4CExtra_shift[34],
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reduced4CExtra_shift[35],
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reduced4CExtra_shift[36]};
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assign io_mulAddA = {_rawA_out_sig_T, io_a[51:0]};
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assign io_mulAddB = {_rawB_out_sig_T, io_b[51:0]};
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assign io_mulAddC = mainAlignedSigC[108:3];
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assign io_toPostMul_isSigNaNAny =
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rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | rawC_isNaN & ~(io_c[51]);
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assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;
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assign io_toPostMul_isInfA = rawA_isSpecial & ~(io_a[61]);
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assign io_toPostMul_isZeroA = ~_rawA_out_sig_T;
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assign io_toPostMul_isInfB = rawB_isSpecial & ~(io_b[61]);
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assign io_toPostMul_isZeroB = ~_rawB_out_sig_T;
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assign io_toPostMul_signProd = signProd;
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assign io_toPostMul_isNaNC = rawC_isNaN;
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assign io_toPostMul_isInfC = rawC_isSpecial & ~(io_c[61]);
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assign io_toPostMul_isZeroC = ~_rawC_out_sig_T;
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assign io_toPostMul_sExpSum =
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CIsDominant ? {1'h0, io_c[63:52]} : _sExpAlignedProd_T_1[12:0] - 13'h35;
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assign io_toPostMul_doSubMags = doSubMags;
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assign io_toPostMul_CIsDominant = CIsDominant;
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assign io_toPostMul_CDom_CAlignDist = CAlignDist[5:0];
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assign io_toPostMul_highAlignedSigC = mainAlignedSigC[163:109];
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assign io_toPostMul_bit0AlignedSigC =
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doSubMags
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? (&(mainAlignedSigC[2:0])) & _GEN == 13'h0
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: (|{mainAlignedSigC[2:0], _GEN});
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endmodule
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