4fa38e35bd70ad546fcf22b2a0baef100e1f9f35
3 Commits
| Author | SHA1 | Message | Date | |
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 onur
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4fa38e35bd |
Fix the RF launch: relieve the planes under J2 and put the ESD on the line
The 0.164/0.200 CPWG geometry was fine; the calculation just stopped at the trace and never covered the connector launch, which is where the real discontinuity was. J2's centre land is 1.5 mm wide because that is what the connector's centre pin needs mechanically. Sitting on solid L2_GND only 0.0994 mm below, that land is a 10.7 ohm transmission line, not a 50 ohm one. The 1.84 mm of it over the plane is 6.7 degrees at L1 and reflects 12 dB (VSWR 1.67) - by far the worst discontinuity in the chain, and worse than everything the carefully built 0.164 mm line downstream avoids. RF_LAUNCH_RELIEF voids L2_GND and L3_SIG under the land, (172.35, 40.95) to (175.10, 43.05). The reference drops to L4_PWR - VCC3V0_RF, an AC ground - 0.587 mm below, which raises the launch to 37 ohm and 30 dB. L3 carried no pour and no copper there, so only L2 actually had to go; the area covers L3 as well so a later edit cannot fill the gap back in. It stops where the land ends and the 0.164 mm line begins, verified: L2 GND is absent across the whole land and present again at x = 172.0 and inboard. D1's ESD clamp sat at the end of a 1.34 mm spur, where its 0.3 pF presented -j228 ohm and cost 3.4 dB for nothing. D1 is rotated onto the run at (171.30, 42.416) so pad 1 overlaps the line directly and pad 2 lands in the RF ground pour; the spur is deleted. Return loss, worst term first: SMA launch land 12.0 -> 30.0 dB (10.7 -> 37.0 ohm) D1 ESD clamp 19.2 -> 22.6 dB (now just the part's own 0.3 pF) C85 DNP tuning stub 25.5 dB unchanged, intentional provision C84 DNP land in line 30.1 dB unchanged, negligible worst-case coherent 7.0 -> 14.4 dB The dominant term is now a component choice rather than a layout defect. Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group, parity unchanged at the 402 pre-existing warnings, RF still 10 segments all on F.Cu at exactly 0.164 mm. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d |
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onur
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1ea2bc64ac |
Add the missing TPS2121 status pull-up (R108) and correct the power-mux docs
The power mux's status output had no pull-up, which broke the USB current budget interlock. TPS2121 ST is an open-drain output; the datasheet lists RST = 6-20 kOhm under Recommended Operating Conditions, alongside RILM, so it is an external part. ST is driven low only while IN2 (the J3 external 5 V header) is sourcing OUT, and is high impedance whenever IN1 (the J7 USB-C input) is sourcing. U10 gate 2 inverts MUX_ST into EXT_SELECTED, and MAIN_EN = USB_3A_OK OR EXT_SELECTED enables the 15 A core buck. With MUX_ST floating on USB-C power, a drift low asserts MAIN_EN no matter what the TUSB320 advertised, so the board would try to bring up the core rail on a 500 mA port. Every other open-drain net here already has its pull-up (R7/R8, R30, R33/R34, R98/R104/R105/R106); this one was missed. R108 (10 k, VCC3V3_AUX -> MUX_ST) is appended at the end of design_data.py rather than beside the mux: reference designators are assigned in call order, so inserting it mid-file would renumber every later resistor and invalidate the routed board. Placed at (53.0, 101.6), 2.4 mm from the U10 gate it holds up, on a site checked clear of existing copper, and routed with close_remaining.py. Also corrects POWER_TREE.md, which credited PR1 for giving the external input priority. PR1 = GND actually *disables* priority mode; CP2 (tied to VCC3V3_AUX) is what selects IN2. Since CP2 derives from the mux's own output the behaviour is two-phase - highest-voltage wins at cold start, IN2 unconditionally once the aux rail is up - so with both inputs connected there can be one seamless switchover at startup. Documented, with the numbers: both eFuses UV 3.98 V / OV 5.80 V, ILIM 2.69 A (USB-C) and 4.04 A (header), mux OV 5.69 V / ILIM 4.5 A. The two inputs are never summed: both eFuses block reverse current and the mux bonds exactly one input at a time. board_routed.kicad_sch/.kicad_sym are now gitignored byte copies of the tracked schematic; kicad-cli needs them beside the board for --schematic-parity, and deleting them in the previous commit had silently disabled that check. Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group, schematic parity unchanged at the 402 pre-existing warnings. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d |
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onur
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95609a6b6a |
Complete the routing: 0 DRC violations, 0 unconnected
The board now routes end to end. Every net carrying two or more pads is a single connected copper group (216 nets, 1175 pads); kicad-cli reports 0 DRC violations and 0 unconnected items with zones refilled. Freerouting was never the blocker. The 14 remaining opens were three separate defects: 1. Obstacles in route_local_power.py modelled every pad as its axis-aligned bounding box. A 0.8-mm BGA dogbone site sits diagonally between four lands: true clearance 0.1407 mm, but the box test measured 0.4 mm from the box edge and rejected it, so no via could be placed anywhere in the Ti375 escape field. Replaced with an exact rounded-rectangle model, validated against KiCad's own SHAPE::Collide to 0.00 um over 14850 samples. Same 0 DRC and one fewer unconnected at the route_local_power stage. 2. CLOCK's 0.15-mm clearance cannot physically escape the BGA: two adjacent 0.45-mm dogbone vias on 0.8-mm pitch leave a 0.35-mm channel and a 0.10-mm trace needs 0.40 mm. HARD_TCK and MAX_SCLK could never leave the package. New rule "Ti375 escape field copper clearance" relaxes clearance to the 0.10 mm this field already uses, only where both objects are inside U1's courtyard. The clock trunk keeps 0.15 mm outside it. 3. RF_NO_DIGITAL was a rectangle reaching 7 mm past the RF line, covering the MAX2771's whole digital pin field and forcing every U21 output onto F.Cu alone. Narrowed to the corridor generate_pcb.py already reserves as TEMP_RF_LINE (y <= 43.7), clearing RF copper by 1.1 mm. The RF return path is guaranteed by the unrouted L2/L7 ground planes, not by this area. scripts/close_remaining.py replaces the ad-hoc residual scripts: a multi-layer maze over (x, y, layer) at 0.1 mm on all five routable layers, seeded from all copper of both groups, exact clearances, 0.10-mm necking inside the escape field, and reversible rip-up that rolls back entirely if a displaced net cannot be put back. ~150 s for the whole board. Also removes the regenerable intermediate boards, one-off session logs and the superseded residual scripts, and tracks board_routed.* as the deliverable. The 402 schematic-parity warnings are pre-existing and unchanged: 199 auto-named unconnected pins, 199 footprint library-nickname mismatches, and 4 mounting holes with no symbol. None affects connectivity or fabrication. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d |