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95609a6b6a527fbc08f1718a915090182cf62810
pcb/outputs/bom.csv
T
onur 95609a6b6a Complete the routing: 0 DRC violations, 0 unconnected 
The board now routes end to end. Every net carrying two or more pads is a
single connected copper group (216 nets, 1175 pads); kicad-cli reports 0 DRC
violations and 0 unconnected items with zones refilled.

Freerouting was never the blocker. The 14 remaining opens were three separate
defects:

1. Obstacles in route_local_power.py modelled every pad as its axis-aligned
   bounding box. A 0.8-mm BGA dogbone site sits diagonally between four lands:
   true clearance 0.1407 mm, but the box test measured 0.4 mm from the box edge
   and rejected it, so no via could be placed anywhere in the Ti375 escape
   field. Replaced with an exact rounded-rectangle model, validated against
   KiCad's own SHAPE::Collide to 0.00 um over 14850 samples. Same 0 DRC and one
   fewer unconnected at the route_local_power stage.

2. CLOCK's 0.15-mm clearance cannot physically escape the BGA: two adjacent
   0.45-mm dogbone vias on 0.8-mm pitch leave a 0.35-mm channel and a 0.10-mm
   trace needs 0.40 mm. HARD_TCK and MAX_SCLK could never leave the package.
   New rule "Ti375 escape field copper clearance" relaxes clearance to the
   0.10 mm this field already uses, only where both objects are inside U1's
   courtyard. The clock trunk keeps 0.15 mm outside it.

3. RF_NO_DIGITAL was a rectangle reaching 7 mm past the RF line, covering the
   MAX2771's whole digital pin field and forcing every U21 output onto F.Cu
   alone. Narrowed to the corridor generate_pcb.py already reserves as
   TEMP_RF_LINE (y <= 43.7), clearing RF copper by 1.1 mm. The RF return path
   is guaranteed by the unrouted L2/L7 ground planes, not by this area.

scripts/close_remaining.py replaces the ad-hoc residual scripts: a multi-layer
maze over (x, y, layer) at 0.1 mm on all five routable layers, seeded from all
copper of both groups, exact clearances, 0.10-mm necking inside the escape
field, and reversible rip-up that rolls back entirely if a displaced net cannot
be put back. ~150 s for the whole board.

Also removes the regenerable intermediate boards, one-off session logs and the
superseded residual scripts, and tracks board_routed.* as the deliverable.

The 402 schematic-parity warnings are pre-existing and unchanged: 199
auto-named unconnected pins, 199 footprint library-nickname mismatches, and 4
mounting holes with no symbol. None affects connectivity or fabrication.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
2026-09-01 11:58:41 +03:00

213 lines
24 KiB
CSV
Raw Blame History

Reference,Qty,Value,Manufacturer,MPN,Footprint,Assembly,DNP,Description
"C1,C129",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TUSB320 local bypass
"C10,C11",2,47uF,Murata,GRM32ER70J476ME19L,Capacitor_SMD:C_1210_3225Metric,SMT,no,5-V system bulk
C100,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,16.368-MHz TCXO bypass
C101,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Clock-rail local bulk
C102,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,40-MHz oscillator bypass
C103,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata V3P3 HF bypass
C104,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata V3P3 local capacitor
C105,1,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata required VREGA2 capacitor
C106,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata required VREGD capacitor
C107,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Murata VDDIO bypass
"C108,C109",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FT4232H VCCIO/VREGIN bypass
"C110,C111",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FT4232H VCORE bypass
C112,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FT4232H regulator output capacitor
C113,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI VPHY bypass
C114,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI VPLL bypass
C115,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI oscillator local bypass
C116,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,FTDI EEPROM bypass
C117,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Additional FT4232H channel-A VCCIO bypass
C118,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Configuration flash bypass
C119,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Configuration flash local bulk
C12,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Power-qualification logic local bypass
C120,1,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS3808 SENSE transient filter
C121,1,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Manual/external reset cable-noise filter
C122,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS3808 local bypass
C123,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,SN74LVC244A local bypass
C124,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,SN74LVC1G125 local bypass
C125,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,SN74LVC1G07 local bypass
C126,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Power-good open-drain buffer local bypass
C127,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,External-reset open-drain buffer local bypass
C128,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,All-rail-valid logic local bypass
C13,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Power qualification logic bypass
C14,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U12 local input capacitor
C15,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U12 low-noise LDO output capacitor
C16,1,1.8nF,Murata,GRM155R71H182KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS6287B calculated compensation CC
C17,1,10pF,Murata,GRM1555C1H100JA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS6287B HF compensation bypass CC2
"C18,C19,C20,C21",4,22uF,Murata,GCM31CR71A226KE02L,Capacitor_SMD:C_1206_3216Metric,SMT,no,Core buck butterfly input capacitor
C2,1,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,USB shield HF coupling
"C22,C23,C24,C25",4,100uF,Murata,GRT32EC70J107ME13L,Capacitor_SMD:C_1210_3225Metric,SMT,no,"Core output; 400-uF nominal, >=195-uF effective target"
"C26,C27",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U14 input capacitor
"C28,C29",2,22uF,Murata,GRM21BZ70J226ME44L,Capacitor_SMD:C_0805_2012Metric,SMT,no,U14 output capacitor
"C3,C6",2,4.7nF,Murata,GRM155R71H472KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,eFuse output slew control
"C30,C31",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U15 input capacitor
"C32,C33",2,22uF,Murata,GRM21BZ70J226ME44L,Capacitor_SMD:C_0805_2012Metric,SMT,no,U15 output capacitor
C34,1,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,LM3880 bypass
C35,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U17 local input capacitor
C36,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U17 low-noise LDO output capacitor
C37,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U18 local input capacitor
C38,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U18 low-noise LDO output capacitor
C39,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U19 local input capacitor
"C4,C7",2,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,eFuse local input bypass
C40,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U19 low-noise LDO output capacitor
C41,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U20 local input capacitor
C42,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,U20 low-noise LDO output capacitor
"C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55,C56,C57,C58,C59,C60",18,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 core/VCCA/VDD_SOC HF bypass
"C5,C8",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,eFuse local output bypass
"C61,C62,C63,C64",4,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 core local bulk
"C65,C66,C67,C68,C69,C70",6,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 VCCAUX/HSIO/config bypass
"C71,C72",2,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 1.8-V local bulk
"C73,C74,C75,C76",4,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 HVIO bank bypass on VCC3V3
C77,1,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 I/O-rail bulk on VCC3V3
"C78,C79,C80,C81",4,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 HVIO bank bypass on VCC3V0_DIG
C82,1,10uF,Murata,GRM188R60J106ME47D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Ti375 I/O-rail bulk on VCC3V0_DIG
C83,1,27pF,Murata,600L270JT200T,board:Kyocera_600L_0402,SMT,no,High-Q 200-V C0G GNSS RF DC block
C84,1,DNP,Murata,,Capacitor_SMD:C_0402_1005Metric,SMT,yes,RF tuning shunt C1
C85,1,DNP,Murata,,Capacitor_SMD:C_0402_1005Metric,SMT,yes,RF tuning shunt C2
C86,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Bias-switch input bypass
C87,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,Bias-switch output bypass before choke
C88,1,15pF,Murata,GRM1555C1H150JA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 PLL loop-filter shunt capacitor
C89,1,750pF,Murata,GRM1555C1H751JA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 PLL loop integrating capacitor
C9,1,10nF,Murata,GRM155R71H103KA88D,Capacitor_SMD:C_0402_1005Metric,SMT,no,TPS2121 soft-start
C90,1,10nF,Murata,GRM155R71H103KA88D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 external reference AC coupling
"C91,C92,C93,C94,C95",5,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_RF bypass
C96,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_RF bulk
"C97,C98",2,100nF,Murata,GRM155R71A104KA01D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_DIG bypass
C99,1,1uF,Murata,GRM155R60J105KE19D,Capacitor_SMD:C_0402_1005Metric,SMT,no,MAX2771 local VCC3V0_DIG bulk
D1,1,ESD501,Texas Instruments,ESD501DPYR,board:Texas_DPY0002A_X1SON,SMT,no,0.3-pF bidirectional 12-V RF ESD protector
D2,1,RESET ESD,onsemi,ESD5Z3.3T1G,Diode_SMD:D_SOD-523,SMT,no,External-reset connector ESD clamp
FB1,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,IMU supply ferrite isolation
FB2,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,FTDI USB-PHY supply ferrite
FB3,1,600R@100MHz,Murata,BLM15AG601SN1D,Inductor_SMD:L_0402_1005Metric,SMT,no,FTDI PLL supply ferrite
FL1,1,GPS L1/L1C SAW,Kyocera,SF14-1582M5UUS2,board:Kyocera_SF14_5pad,SMT,no,"1565.19-1585.65-MHz SAW, 1.2-dB typical insertion loss"
J1,1,USB-C USB2 sink,GCT,USB4105-GF-A-120,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,SMT,no,"USB 2.0 Type-C receptacle, UFP/sink, debug data only"
J2,1,GPS L1 SMA,Amphenol RF,132289,Connector_Coaxial:SMA_Amphenol_132289_EdgeMount,THT,no,Edge-launch 50-ohm active GNSS antenna input
J3,1,EXT_5V,Phoenix Contact,1935161,"TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal",THT,no,Clearly labelled external regulated 5-V input
J4,1,EXT RESET_N,JST,SM02B-SRSS-TB(LF)(SN),Connector_JST:JST_SH_SM02B-SRSS-TB_1x02-1MP_P1.00mm_Horizontal,SMT,no,External active-low open-drain reset input; JST-SH 1.0-mm
J5,1,ANT BIAS OFF/3V3/5V,Wuerth Elektronik,61300311121,Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical,THT,no,One-shunt hardware antenna bias selection; no shunt is OFF
J7,1,USB-C power input,GCT,USB4105-GF-A-120,Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal,SMT,no,"USB 2.0 Type-C receptacle, UFP/sink, power input only"
"JPMOD1,JPMOD2",2,PMOD 3.3 V,Amphenol ICC,67997-412HLF,board:Digilent_PMOD_2x6_P2.54mm,THT,no,"Digilent 2x6 PMOD: eight 3.3 V GPIO, two GND, two 3.3 V"
"JPMOD3,JPMOD4",2,PMOD 1.8 V,Amphenol ICC,67997-412HLF,board:Digilent_PMOD_2x6_P2.54mm,THT,no,"Digilent 2x6 PMOD: eight 1.8 V GPIO, two GND, two 1.8 V"
L1,1,100nH,Coilcraft,XEL4030-101MEC,board:Coilcraft_XEL4030,SMT,no,"Core inductor: 30-A saturation, 1.5-mohm DCR"
"L2,L3",2,240nH,Murata,DFE201612E-R24M=P2,board:Murata_DFE201612E,SMT,no,TPS62867 manufacturer-recommended 6.6-A inductor
L4,1,56nH,Coilcraft,0402HPH-56NXJRW,Inductor_SMD:L_0402_1005Metric,SMT,no,"L1 bias-tee choke: SRF 2.1 GHz, Q 64, 330 mA"
Q1,1,MMBT3904,onsemi,MMBT3904LT1G,Package_TO_SOT_SMD:SOT-23,SMT,no,Power-good inverter: enables FTDI-to-FPGA buffers only after all rails are valid
"R1,R2,R3,R4,R5",5,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix mandatory 10-kohm 1% reference resistor
R10,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,yes,Optional direct shield bond
R100,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,All-rail-good inverter base-current limiter
R101,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Power-good inverter default-off base pull-down
R102,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,External/manual reset input pull-up
R103,1,1K,Yageo,RC0402FR-071KL,Resistor_SMD:R_0402_1005Metric,SMT,no,External-reset input current and ESD limiting
R104,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,LM3880 final-flag pull-up for all-power logic
R105,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,1.8-V power-good pull-up for all-power logic
R106,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,3.3-V power-good pull-up for all-power logic
"R11,R16",2,232K,Yageo,RC0402FR-07232KL,Resistor_SMD:R_0402_1005Metric,SMT,no,4.0-V nominal eFuse UV divider top
"R12,R17",2,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse UV divider bottom
"R13,R18",2,383K,Yageo,RC0402FR-07383KL,Resistor_SMD:R_0402_1005Metric,SMT,no,5.8-V nominal eFuse OV divider top
"R14,R19",2,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse OV divider bottom
R15,1,1.24K,Yageo,RC0402FR-071K24L,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse RILM=3334/ILIM
R20,1,825R,Yageo,RC0402FR-07825RL,Resistor_SMD:R_0402_1005Metric,SMT,no,eFuse RILM=3334/ILIM
R21,1,442K,Yageo,RC0402FR-07442KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN1 5.75-V OV divider top
R22,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN1 OV divider bottom
R23,1,442K,Yageo,RC0402FR-07442KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN2 5.75-V OV divider top
R24,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 IN2 OV divider bottom
R25,1,22.1K,Yageo,RC0402FR-0722K1L,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS2121 4.5-A typical output limit
R26,1,15K,Yageo,RC0402FR-0715KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS6287B mandatory >=15-kohm EN series resistor
R27,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,Remote positive sense link at FPGA PDN
R28,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,Remote ground sense link at FPGA PDN
R29,1,2.1K,Yageo,RC0402FR-072K1L,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS6287B calculated compensation RZ
R30,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Core buck PG pull-up
R31,1,133K,Yageo,RC0402FR-07133KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS62867 fixed 1.8 V VSET resistor
R32,1,205K,Yageo,RC0402FR-07205KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS62867 fixed 3.3 V VSET resistor
"R33,R34",2,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,LM3880 open-drain flag pull-up
R35,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,FPGA CRESET_N configuration-rail pull-up
R36,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,Sequencer final-flag sense link
R37,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,1.8-V buck power-good sense link
R38,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,3.3-V buck power-good sense link
R39,1,0R,Yageo,RC0402JR-070RL,Resistor_SMD:R_0402_1005Metric,SMT,no,RF tuning series link
R40,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Bias switch follows selected source
R41,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,No-jumper default OFF
R42,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Antenna overcurrent pull-up
R43,1,15K,Yageo,RC0402FR-0715KL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 PLL loop-filter resistor
R44,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,40-MHz ADC-clock source termination
"R45,R46,R47,R48,R49,R50",6,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 source-series digital damping
"R51,R52,R53,R54",4,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 serial/control source damping
R55,1,100K,Yageo,RC0402FR-07100KL,Resistor_SMD:R_0402_1005Metric,SMT,no,MAX2771 remains shut down before FPGA configuration
R56,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,40-MHz FPGA-clock source termination
"R57,R58,R59",3,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,SafeSPI source-series damping
"R6,R107",2,900K,Yageo,RC0402FR-07909KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 VBUS_DET current limiter
R60,1,22R,Yageo,RC0402FR-0722RL,Resistor_SMD:R_0402_1005Metric,SMT,no,SafeSPI MISO source damping at IMU
R61,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Hold IMU reset until FPGA releases it
R62,1,27R,Yageo,RC0402FR-0727RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI USB D+ series termination
R63,1,27R,Yageo,RC0402FR-0727RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI USB D- series termination
R64,1,12K,Yageo,RC0402FR-0712KL,Resistor_SMD:R_0402_1005Metric,SMT,no,"FT4232H USB PHY reference resistor, 1%"
R65,1,4.7K,Yageo,RC0402FR-074K7L,Resistor_SMD:R_0402_1005Metric,SMT,no,Self-powered VBUS-present reset divider top
R66,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Self-powered VBUS-present reset divider bottom
R67,1,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI oscillator source termination
R68,1,2.2K,Yageo,RC0402FR-072K2L,Resistor_SMD:R_0402_1005Metric,SMT,no,EEPROM shared-data isolation
R69,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,EEPROM DO pull-up
R7,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 open-drain OUT1 pull-up
"R70,R71,R72,R73",4,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI interface-1 hard-JTAG source damping
"R74,R90,R91,R92",4,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix-required hard-JTAG weak pull-up
"R75,R76,R77,R78,R79,R80,R81,R82,R83",9,33R,Yageo,RC0402FR-0733RL,Resistor_SMD:R_0402_1005Metric,SMT,no,FT4232H channel signal damping
R8,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TUSB320 open-drain OUT2 pull-up
R84,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Configuration flash CS pull-up
R85,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix mandatory TEST_N weak pull-up
R86,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix mandatory CSI weak pull-up
"R87,R88",2,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Configuration flash hold/write-protect pull-up
R89,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Efinix-required CDONE open-drain pull-up
R9,1,1M,Yageo,RC0402FR-071ML,Resistor_SMD:R_0402_1005Metric,SMT,no,USB shield bleed
"R93,R94,R95,R96",4,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,RISC-V JTAG idle-state pull-up
R97,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,FTDI FPGA-reset request default release
R98,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,TPS3808 open-drain power-good pull-up
R99,1,10K,Yageo,RC0402FR-0710KL,Resistor_SMD:R_0402_1005Metric,SMT,no,Keep FTDI-to-FPGA buffers disabled until power-good
SW1,1,FPGA RESET,Omron,B3U-1000P,Button_Switch_SMD:SW_SPST_B3U-1000P,SMT,no,User-accessible momentary FPGA configuration reset
TP1,1,U7 FLT,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP10,1,3V3,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP11,1,RF 3V0,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP12,1,DIG 3V0,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP13,1,CRESET_N,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP14,1,CDONE,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP15,1,GND,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP2,1,U8 FLT,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP3,1,ANT OC,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP4,1,USB VBUS,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP5,1,EXT 5V,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP6,1,SYS 5V,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP7,1,AUX 3V3,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP8,1,CORE 0V95,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
TP9,1,1V8,,,TestPoint:TestPoint_Pad_D1.0mm,SMT,no,Local labelled SMT bring-up test pad
U1,1,Ti375C529C3,Efinix,Ti375C529C3,Package_BGA:BGA-529_19x19mm_Layout23x23_P0.8mm,SMT,no,"Titanium Ti375 FPGA, commercial standard-power 0.95-V option, C529"
U10,1,SN74LVC2G02,Texas Instruments,SN74LVC2G02DCUR,Package_SO:VSSOP-8_2.3x2mm_P0.5mm,SMT,no,USB 3-A advertisement NOR decode and mux-status inversion
U11,1,SN74LVC1G32,Texas Instruments,SN74LVC1G32DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Main-rail enable OR: qualified 3-A USB or selected external 5 V
U12,1,TPS7A2033,Texas Instruments,TPS7A2033PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Always-on 300-mA auxiliary 3.3-V LDO
U13,1,TPS6287B15HA0,Texas Instruments,TPS6287B15HA0WRZVR,board:Texas_RZV0024A_WQFN24,SMT,no,"15-A synchronous 0.95-V FPGA core/VCCA/VDD_SOC buck, fixed PWM"
U14,1,TPS62867 1.8 V,Texas Instruments,TPS62867RQYR,board:Texas_RQY0009A_VQFN9,SMT,no,6-A synchronous 1.8 V FPGA auxiliary/I/O buck
U15,1,TPS62867 3.3 V,Texas Instruments,TPS62867RQYR,board:Texas_RQY0009A_VQFN9,SMT,no,6-A synchronous 3.3 V FPGA auxiliary/I/O buck
U16,1,LM3880-1AA,Texas Instruments,LM3880MF-1AA/NOPB,Package_TO_SOT_SMD:SOT-23-6,SMT,no,"Three-rail sequencer, 10-ms delay per rail"
U17,1,TPS7A2030,Texas Instruments,TPS7A2030PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Dedicated low-noise 3.0-V MAX2771 analog LDO
U18,1,TPS7A2030,Texas Instruments,TPS7A2030PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Dedicated low-noise 3.0-V MAX2771 digital and FPGA-bank LDO
U19,1,TPS7A2030,Texas Instruments,TPS7A2030PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Dedicated low-noise 3.0-V oscillator LDO
U2,1,FT4232H-56Q,FTDI,FT4232H-56Q-REEL,board:FTDI_VQFN56_EP5p9,SMT,no,Quad high-speed USB bridge; all four channels assigned
U20,1,TPS7A2033,Texas Instruments,TPS7A2033PDBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Clean 3.3-V active-antenna bias LDO
U21,1,MAX2771,Analog Devices,MAX2771ETI+,Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.25x3.25mm,SMT,no,GNSS receiver; both LNAs disabled; direct high-band mixer input
U22,1,SCH16T-K01-1,Murata,SCH16T-K01-1,board:Murata_SCH16T_K01,SMT,no,"Six-DoF SafeSPI IMU, exact K01-1 variant"
U23,1,16.368 MHz TCXO,Epson,X1G005441030125,board:Epson_TG2016SMN,SMT,no,TG2016SMN clipped-sine ±0.5-ppm MAX2771 reference
U24,1,40.000 MHz XO,Epson,X1G004171041100,Oscillator:Oscillator_SMD_SeikoEpson_SG210-4Pin_2.5x2.0mm,SMT,no,SG-210STF ±25-ppm CMOS FPGA/system ADC oscillator
U25,1,12.000 MHz XO,ECS,ECS-2520MV-120-BN-TR,Oscillator:Oscillator_SMD_ECS_2520MV-xxx-xx-4Pin_2.5x2.0mm,SMT,no,Current-production 12-MHz CMOS FT4232H clock
U26,1,512-Mbit QSPI flash,ISSI,IS25WP512M-JLLE,Package_SON:WSON-8-1EP_6x5mm_P1.27mm_EP3.4x4.3mm,SMT,no,1.8-V 512-Mbit FPGA active-serial configuration flash
U27,1,TPS22944,Texas Instruments,TPS22944DCKR,Package_TO_SOT_SMD:SOT-353_SC-70-5,SMT,no,Fixed 100-mA current-limited active-antenna load switch
U28,1,TPS3808G30,Texas Instruments,TPS3808G30DBVR,Package_TO_SOT_SMD:SOT-23-6,SMT,no,3.0-V FPGA-bank supervisor; open-drain reset with 20-ms release delay
U29,1,SN74LVC244A,Texas Instruments,SN74LVC244APWR,Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm,SMT,no,Ioff-protected FPGA-input buffer; automatically isolates when FPGA 3.3 V is off
U3,1,93LC56B x16,Microchip,93LC56BT-I/OT,Package_TO_SOT_SMD:SOT-23-6,SMT,no,"FTDI descriptor/channel-mode EEPROM, fixed 16-bit organization"
U30,1,SN74LVC1G125,Texas Instruments,SN74LVC1G125DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Ioff-protected tri-state debug-GPIO buffer powered from FPGA 3.3 V
U31,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain FTDI reset request into FPGA CRESET_N
U32,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain all-rail-valid translation into FPGA CRESET_N
U33,1,SN74LVC1G07,Texas Instruments,SN74LVC1G07DBVR,Package_TO_SOT_SMD:SOT-23-5,SMT,no,Open-drain external/manual reset isolation into FPGA CRESET_N
U34,1,SN74LVC08A,Texas Instruments,SN74LVC08APWR,Package_SO:TSSOP-14_4.4x5mm_P0.65mm,SMT,no,Always-on all-rail power-valid logic for reset release and debug isolation
U35,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,SMT,no,USB Type-C port controller in UFP GPIO mode for the power input; integrated Rd on CC1/CC2; OUT1/OUT2 3-A advertisement drives U10/U11 MAIN_EN gating
U5,1,TUSB320LAI,Texas Instruments,TUSB320LAIRSW(R),Package_DFN_QFN:Texas_X2QFN-12_1.6x1.6mm_P0.4mm,SMT,no,USB Type-C port controller in UFP GPIO mode; integrated Rd on CC1/CC2; current-advertisement outputs unused since this port never sources SYS5
U6,1,TPD2EUSB30A,Texas Instruments,TPD2EUSB30ADRTR,Package_TO_SOT_SMD:Texas_DRT-3,SMT,no,Low-capacitance USB 2.0 ESD protection
"U7,U8",2,TPS259470A,Texas Instruments,TPS259470ARPWR,board:Texas_RPW0010A_QFN10,SMT,no,True-reverse-blocking eFuse; UV/OV/current/inrush protection
U9,1,TPS2121,Texas Instruments,TPS2121RUXR,board:Texas_RUX0012A_VQFN12,SMT,no,4.5-A power mux; external input wins near-equal valid 5-V inputs
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