onur
af7c43b2a8
The Ti375 fanout could not be resolved with three routing layers, so L5 stops being a dedicated 1.8-V plane and becomes a signal layer. No rail owns a whole layer any more: the supplies are split into zone islands on L4 and L6, L2 and L7 stay solid and completely unrouted, and F.Cu, L3, L5 and B.Cu are all available for signals. Routing is staged rather than handed to the autorouter wholesale. The BGA escape, the buck high-current loops, plane stitching and the local power completion all run first and are locked; Freerouting then sees only the ordinary digital classes, with everything else present as fixed copper. finalize_routing.py installs the audited RF and USB geometry and closes whatever the autorouter left. Four bugs behind the routing failures, all of them the same shape - a layer list written down instead of read from the board, which was correct while L5 was a plane and silently wrong afterwards: - export_routing_stage.py emitted via keepouts for three layers only, so every existing via was invisible to the router on L5. It drove traces straight through them: 102 shorting_items in DRC. - route_local_power.py never used L5 at all, and picked up escape vias on two layers instead of all four. - add_rf_ground() judged fence positions against vias and pads but not tracks. It runs after the session import, when that region already has routed copper, and dropped a ground via on top of a signal trace. route_local_power.py also grew a via cloud on every rail: reaching a plane counted as progress even when it merged nothing, so the same pad collected a via per pass, 0.4 mm further out each time. Progress is now measured by the group count actually falling, and groups already sitting on their plane are skipped. That removed 404 redundant vias. The MAX2771 PLL loop filter was spread across three corners of the package, which forced the charge-pump node onto an inner layer under the GPS front end. All three parts now sit in the pocket at U21's north-west corner and the net stays on F.Cu. A permanent RF_NO_DIGITAL area plus a scoped rule keeps that region free of non-power copper on L3/L5/L6/B.Cu, and the local router enforces the same restriction, since it is the one stage that runs after the temporary keepout is deleted. Also enables the solder-mask bridge check that was switched off board-wide; the board passes it with no violations. Final board: DRC clean - no shorts, clearance, disallowed-item or dangling-copper violations - with 26 unconnected endpoints left. Routing is spread 37% L3, 27% F.Cu, 26% L5, 10% B.Cu over 6548 mm and 971 vias. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
32 lines
1.5 KiB
Markdown
32 lines
1.5 KiB
Markdown
# Çıktılar
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Bu klasör build/routing çalışma alanıdır. Repository'de yalnızca güncel ve
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anlamlı teslim çıktıları tutulur:
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- `bom.csv`: ayrıntılı mühendislik BOM'u.
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- `jlcpcb_bom.csv`: montaj servisi için sadeleştirilmiş BOM.
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- `erc_final_reset.rpt`: güncel şema ERC raporu; 0 ihlal.
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- `drc_final_placement.rpt`: unrouted placement DRC raporu.
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- `drc_power_local.rpt`: sinyal routing'inden önceki güç katı DRC raporu.
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- `drc_final_routed.rpt`: routed kart DRC raporu.
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- `board_final_reset_top.png`: güncel üst görünüm.
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Routing çalışma dosyaları:
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- `signal_stage.dsn` / `signal_stage.ses`: autorouter'a verilen ve ondan alınan
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sinyal katı. Sadece `board_power_local.kicad_pcb` ile birlikte anlamlıdır.
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- `signal_stage_preview.kicad_pcb`: DSN'e giren bakırın KiCad'de incelenebilir
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hâli.
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- `freerouting_signal.log`: pass başına unrouted/violation sayısı.
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Eski `.dsn`, `.ses`, preview PCB ve ara DRC raporları yeni netlist için
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authoritative değildir. `.dsn` her zaman onu üreten karta bağlıdır: placement,
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güç bakırı veya keepout değiştiğinde export ve routing baştan yapılmalıdır,
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yoksa import edilen sonuç mevcut bakırla çakışır.
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Final routed raporda sıfır açık bağlantı, sıfır clearance/short ve sıfır
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schematic-parity hatası hedeflenir. Unrouted aşamadaki `unconnected_items`,
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`via_dangling` ve `isolated_copper` kayıtları normaldir: sırasıyla henüz
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çekilmemiş bağlantıları, henüz kullanılmayan BGA escape via'larını ve final
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fill'de silinecek plane parçalarını gösterir.
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