Four RF points came back from review. Two were real gaps, two were already
sound but undocumented, and one premise was stale.
Real gap 1 - nothing told the fab this is a controlled-impedance board.
docs/FABRICATION.md now carries the stackup (JLC08161H-3313, layer by layer
with dielectric heights and Er), the two impedance targets (RF50_CPWG 50 ohm at
0.164/0.200 on F.Cu over L2, USB90_DIFF 90 ohm at 0.135/0.150), the process
minima, and an explicit request that the vendor confirm the widths with their
own field solver. It records that JLC models this as
CoatedCoplanarWaveguideWithLowerGnd1B assuming 1.6 mil finished outer copper,
0.6 mil soldermask at Er 3.8 and top width = base - 0.7 mil, and that copper
thickness alone moves this geometry by more than 10 ohm - which is why the
number has to be fixed by the vendor's model rather than ours. It also states
the decision rule: 44 ohm is still 24 dB return loss and not the worst term in
the chain, so the geometry should not be changed unless the vendor reports
below that.
Real gap 2 - the active-antenna requirement was implied everywhere but never
quantified. hardware/README.md and docs/INTERFACES.md now state it plainly:
with both internal LNAs off the mixer input is the first active stage at
10.3 dB NF, so a ~25 dB active antenna gives ~1.65 dB system NF while a passive
antenna puts it above 12 dB and the receiver is unusable. The same section now
explains why the SAW is not optional either.
Documented, not changed - the launch relief. Its ~37 ohm / 30 dB figure is a 2D
quasi-static estimate of a genuinely 3D transition (connector, board edge, pad
overhang) and is now labelled as such, with 3D EM or VNA named as what would
settle it. The unrelieved case was 10.7 ohm / 12 dB, so the improvement holds
regardless of the exact figure.
Documented, not changed - the bias choke. Its 2.1 GHz SRF sits above 1575 MHz,
so the choke is still inductive and the proximity raises |Z| from 554 to about
1270 ohm, which helps a bias tee rather than hurting it. Swept +/-10% on both L
and SRF: |Z| stays above 900 ohm, return loss above 30 dB, insertion loss below
0.003 dB.
Stale premise - the review tied the impedance to "the inconsistent stackup".
That inconsistency was fixed in 791ca5c, and the F.Cu-to-L2 construction that
sets the RF impedance (3313 prepreg, 0.0994 mm, Er 4.1) was in fact identical
in both the old ten-layer and the current eight-layer stacks, so the CPWG
geometry never actually moved.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
The power mux's status output had no pull-up, which broke the USB current
budget interlock.
TPS2121 ST is an open-drain output; the datasheet lists RST = 6-20 kOhm under
Recommended Operating Conditions, alongside RILM, so it is an external part.
ST is driven low only while IN2 (the J3 external 5 V header) is sourcing OUT,
and is high impedance whenever IN1 (the J7 USB-C input) is sourcing. U10 gate 2
inverts MUX_ST into EXT_SELECTED, and MAIN_EN = USB_3A_OK OR EXT_SELECTED
enables the 15 A core buck. With MUX_ST floating on USB-C power, a drift low
asserts MAIN_EN no matter what the TUSB320 advertised, so the board would try
to bring up the core rail on a 500 mA port. Every other open-drain net here
already has its pull-up (R7/R8, R30, R33/R34, R98/R104/R105/R106); this one was
missed.
R108 (10 k, VCC3V3_AUX -> MUX_ST) is appended at the end of design_data.py
rather than beside the mux: reference designators are assigned in call order,
so inserting it mid-file would renumber every later resistor and invalidate the
routed board. Placed at (53.0, 101.6), 2.4 mm from the U10 gate it holds up,
on a site checked clear of existing copper, and routed with close_remaining.py.
Also corrects POWER_TREE.md, which credited PR1 for giving the external input
priority. PR1 = GND actually *disables* priority mode; CP2 (tied to VCC3V3_AUX)
is what selects IN2. Since CP2 derives from the mux's own output the behaviour
is two-phase - highest-voltage wins at cold start, IN2 unconditionally once the
aux rail is up - so with both inputs connected there can be one seamless
switchover at startup. Documented, with the numbers: both eFuses UV 3.98 V /
OV 5.80 V, ILIM 2.69 A (USB-C) and 4.04 A (header), mux OV 5.69 V / ILIM 4.5 A.
The two inputs are never summed: both eFuses block reverse current and the mux
bonds exactly one input at a time.
board_routed.kicad_sch/.kicad_sym are now gitignored byte copies of the tracked
schematic; kicad-cli needs them beside the board for --schematic-parity, and
deleting them in the previous commit had silently disabled that check.
Verified: ERC 0/0, DRC 0 violations, 0 unconnected, every net one copper group,
schematic parity unchanged at the 402 pre-existing warnings.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
The board now routes end to end. Every net carrying two or more pads is a
single connected copper group (216 nets, 1175 pads); kicad-cli reports 0 DRC
violations and 0 unconnected items with zones refilled.
Freerouting was never the blocker. The 14 remaining opens were three separate
defects:
1. Obstacles in route_local_power.py modelled every pad as its axis-aligned
bounding box. A 0.8-mm BGA dogbone site sits diagonally between four lands:
true clearance 0.1407 mm, but the box test measured 0.4 mm from the box edge
and rejected it, so no via could be placed anywhere in the Ti375 escape
field. Replaced with an exact rounded-rectangle model, validated against
KiCad's own SHAPE::Collide to 0.00 um over 14850 samples. Same 0 DRC and one
fewer unconnected at the route_local_power stage.
2. CLOCK's 0.15-mm clearance cannot physically escape the BGA: two adjacent
0.45-mm dogbone vias on 0.8-mm pitch leave a 0.35-mm channel and a 0.10-mm
trace needs 0.40 mm. HARD_TCK and MAX_SCLK could never leave the package.
New rule "Ti375 escape field copper clearance" relaxes clearance to the
0.10 mm this field already uses, only where both objects are inside U1's
courtyard. The clock trunk keeps 0.15 mm outside it.
3. RF_NO_DIGITAL was a rectangle reaching 7 mm past the RF line, covering the
MAX2771's whole digital pin field and forcing every U21 output onto F.Cu
alone. Narrowed to the corridor generate_pcb.py already reserves as
TEMP_RF_LINE (y <= 43.7), clearing RF copper by 1.1 mm. The RF return path
is guaranteed by the unrouted L2/L7 ground planes, not by this area.
scripts/close_remaining.py replaces the ad-hoc residual scripts: a multi-layer
maze over (x, y, layer) at 0.1 mm on all five routable layers, seeded from all
copper of both groups, exact clearances, 0.10-mm necking inside the escape
field, and reversible rip-up that rolls back entirely if a displaced net cannot
be put back. ~150 s for the whole board.
Also removes the regenerable intermediate boards, one-off session logs and the
superseded residual scripts, and tracks board_routed.* as the deliverable.
The 402 schematic-parity warnings are pre-existing and unchanged: 199
auto-named unconnected pins, 199 footprint library-nickname mismatches, and 4
mounting holes with no symbol. None affects connectivity or fabrication.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_012KaTmCCxCEW4awsmXRNT1d
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