max2771 spi liens has been added.
This commit is contained in:
onur
@@ -26,7 +26,7 @@ OBJCOPY := $(CROSS)objcopy
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READELF := $(CROSS)readelf
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MAKE_FLASH_IMAGE := $(SOC_DIR)/software/tools/make_flash_image.py
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.PHONY: help all app bootloader hello pmod-spi-test steval-mki217v1-test gps-system flash-image clean
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.PHONY: help all app bootloader hello pmod-spi-test max2771-spi-test steval-mki217v1-test gps-system flash-image clean
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help:
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@echo "Common Rocket bare-metal software targets:"
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@@ -35,6 +35,7 @@ help:
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@echo " make bootloader # build only BootROM flash bootloader"
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@echo " make hello # build only hello UART app"
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@echo " make pmod-spi-test # build PMOD SPI smoke test app"
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@echo " make max2771-spi-test # build dedicated MAX2771 SPI test app"
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@echo " make steval-mki217v1-test # build STEVAL-MKI217V1 LSM6DSOX polling app"
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@echo " make gps-system # build imported GPS bare-metal app"
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@echo " make flash-image APP=name # build bootloader-readable app flash image"
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@@ -63,6 +64,9 @@ hello:
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pmod-spi-test:
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@make -C pmod_spi_test TOOLCHAIN="$(TOOLCHAIN)" BUILD_DIR="$(OUT_DIR)/pmod_spi_test" BSP_UART_CLOCK_HZ="$(BSP_UART_CLOCK_HZ)" BSP_UART_BAUDRATE="$(BSP_UART_BAUDRATE)" BSP_CLINT_TIMEBASE_HZ="$(BSP_CLINT_TIMEBASE_HZ)" BSP_DTIM_BASE="$(BSP_DTIM_BASE)" BSP_DTIM_SIZE="$(BSP_DTIM_SIZE)" all
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max2771-spi-test:
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@make -C max2771_spi_test TOOLCHAIN="$(TOOLCHAIN)" BUILD_DIR="$(OUT_DIR)/max2771_spi_test" BSP_UART_CLOCK_HZ="$(BSP_UART_CLOCK_HZ)" BSP_UART_BAUDRATE="$(BSP_UART_BAUDRATE)" BSP_CLINT_TIMEBASE_HZ="$(BSP_CLINT_TIMEBASE_HZ)" BSP_DTIM_BASE="$(BSP_DTIM_BASE)" BSP_DTIM_SIZE="$(BSP_DTIM_SIZE)" all
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steval-mki217v1-test:
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@make -C steval_mki217v1_test TOOLCHAIN="$(TOOLCHAIN)" BUILD_DIR="$(OUT_DIR)/steval_mki217v1_test" BSP_UART_CLOCK_HZ="$(BSP_UART_CLOCK_HZ)" BSP_UART_BAUDRATE="$(BSP_UART_BAUDRATE)" BSP_CLINT_TIMEBASE_HZ="$(BSP_CLINT_TIMEBASE_HZ)" BSP_DTIM_BASE="$(BSP_DTIM_BASE)" BSP_DTIM_SIZE="$(BSP_DTIM_SIZE)" all
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@@ -0,0 +1,130 @@
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#include "bsp/max2771_spi.h"
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#include "bsp/mmio.h"
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#include "bsp/soc.h"
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#define MAX2771_COMMAND (BSP_MAX2771_SPI_BASE + 0x00u)
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#define MAX2771_WRITE_DATA (BSP_MAX2771_SPI_BASE + 0x04u)
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#define MAX2771_READ_DATA (BSP_MAX2771_SPI_BASE + 0x08u)
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#define MAX2771_STATUS (BSP_MAX2771_SPI_BASE + 0x0cu)
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#define MAX2771_INPUT_CLOCK (BSP_MAX2771_SPI_BASE + 0x10u)
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#define MAX2771_SCLK (BSP_MAX2771_SPI_BASE + 0x14u)
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#define MAX2771_HALF_PERIOD (BSP_MAX2771_SPI_BASE + 0x18u)
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#define MAX2771_IDENT (BSP_MAX2771_SPI_BASE + 0x1cu)
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#define MAX2771_STATUS_READY 0x1u
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#define MAX2771_STATUS_BUSY 0x2u
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#define MAX2771_COMMAND_READ 0x100u
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#define MAX2771_IDENT_VALUE 0x4d415831u
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#define MAX2771_TIMEOUT_US 1000u
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static bsp_max2771_status_t max2771_wait_ready(void)
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{
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uint64_t timeout_ticks =
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((uint64_t)BSP_CLINT_TIMEBASE_HZ * MAX2771_TIMEOUT_US + 999999u) /
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1000000u;
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if (timeout_ticks == 0u) {
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timeout_ticks = 1u;
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}
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const uint64_t start = bsp_read64(BSP_CLINT_MTIME);
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while ((bsp_read32(MAX2771_STATUS) & MAX2771_STATUS_READY) == 0u) {
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if ((bsp_read64(BSP_CLINT_MTIME) - start) >= timeout_ticks) {
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return BSP_MAX2771_ERR_TIMEOUT;
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}
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}
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return BSP_MAX2771_OK;
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}
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uint32_t bsp_max2771_status(void)
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{
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return bsp_read32(MAX2771_STATUS);
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}
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uint32_t bsp_max2771_input_clock_hz(void)
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{
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return bsp_read32(MAX2771_INPUT_CLOCK);
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}
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uint32_t bsp_max2771_sclk_hz(void)
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{
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return bsp_read32(MAX2771_SCLK);
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}
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uint32_t bsp_max2771_half_period_cycles(void)
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{
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return bsp_read32(MAX2771_HALF_PERIOD);
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}
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bsp_max2771_status_t bsp_max2771_spi_init(void)
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{
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if (bsp_read32(MAX2771_IDENT) != MAX2771_IDENT_VALUE) {
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return BSP_MAX2771_ERR_IP;
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}
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const uint32_t input_hz = bsp_max2771_input_clock_hz();
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const uint32_t sclk_hz = bsp_max2771_sclk_hz();
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const uint32_t half_cycles = bsp_max2771_half_period_cycles();
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if ((input_hz == 0u) || (half_cycles == 0u) ||
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(sclk_hz == 0u) || (sclk_hz > BSP_MAX2771_MAX_SCLK_HZ) ||
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(sclk_hz != (input_hz / (2u * half_cycles)))) {
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return BSP_MAX2771_ERR_CLOCK;
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}
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#ifdef BSP_MAX2771_INPUT_CLOCK_HZ
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if (input_hz != (uint32_t)BSP_MAX2771_INPUT_CLOCK_HZ) {
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return BSP_MAX2771_ERR_CLOCK;
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}
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#endif
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return max2771_wait_ready();
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}
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bsp_max2771_status_t bsp_max2771_write(uint8_t address, uint32_t value)
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{
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if (address > BSP_MAX2771_MAX_REGISTER) {
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return BSP_MAX2771_ERR_ARGUMENT;
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}
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bsp_max2771_status_t status = max2771_wait_ready();
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if (status != BSP_MAX2771_OK) {
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return status;
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}
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bsp_write32(MAX2771_WRITE_DATA, value);
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bsp_write32(MAX2771_COMMAND, (uint32_t)address);
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return max2771_wait_ready();
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}
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bsp_max2771_status_t bsp_max2771_read(uint8_t address, uint32_t *value)
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{
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if ((address > BSP_MAX2771_MAX_REGISTER) || (value == 0)) {
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return BSP_MAX2771_ERR_ARGUMENT;
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}
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bsp_max2771_status_t status = max2771_wait_ready();
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if (status != BSP_MAX2771_OK) {
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return status;
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}
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bsp_write32(MAX2771_COMMAND, MAX2771_COMMAND_READ | (uint32_t)address);
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status = max2771_wait_ready();
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if (status == BSP_MAX2771_OK) {
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*value = bsp_read32(MAX2771_READ_DATA);
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}
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return status;
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}
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bsp_max2771_status_t bsp_max2771_write_verified(uint8_t address, uint32_t value)
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{
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bsp_max2771_status_t status = bsp_max2771_write(address, value);
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if (status != BSP_MAX2771_OK) {
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return status;
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}
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uint32_t readback = 0u;
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status = bsp_max2771_read(address, &readback);
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if (status != BSP_MAX2771_OK) {
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return status;
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}
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return (readback == value) ? BSP_MAX2771_OK : BSP_MAX2771_ERR_VERIFY;
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}
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@@ -0,0 +1,34 @@
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#ifndef BSP_MAX2771_SPI_H
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#define BSP_MAX2771_SPI_H
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#include <stdint.h>
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#define BSP_MAX2771_REGISTER_COUNT 11u
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#define BSP_MAX2771_MAX_REGISTER 0x0au
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#define BSP_MAX2771_MAX_SCLK_HZ 4000000u
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typedef enum {
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BSP_MAX2771_OK = 0,
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BSP_MAX2771_ERR_ARGUMENT = -1,
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BSP_MAX2771_ERR_TIMEOUT = -2,
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BSP_MAX2771_ERR_IP = -3,
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BSP_MAX2771_ERR_CLOCK = -4,
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BSP_MAX2771_ERR_VERIFY = -5
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} bsp_max2771_status_t;
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/* Validate the dedicated MMIO IP, its board clock, and its idle state. */
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bsp_max2771_status_t bsp_max2771_spi_init(void);
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/* Execute one complete, hardware-timed 48-SCLK MAX2771 transaction. */
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bsp_max2771_status_t bsp_max2771_write(uint8_t address, uint32_t value);
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bsp_max2771_status_t bsp_max2771_read(uint8_t address, uint32_t *value);
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/* Write then read one register. The readback must equal the written value. */
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bsp_max2771_status_t bsp_max2771_write_verified(uint8_t address, uint32_t value);
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uint32_t bsp_max2771_input_clock_hz(void);
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uint32_t bsp_max2771_sclk_hz(void);
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uint32_t bsp_max2771_half_period_cycles(void);
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uint32_t bsp_max2771_status(void);
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#endif
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@@ -6,6 +6,7 @@
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#define BSP_UART_BASE 0x10013000UL
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#define BSP_SPI_BASE 0x10014000UL
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#define BSP_PMOD_SPI_BASE 0x10015000UL
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#define BSP_MAX2771_SPI_BASE 0x10016000UL
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#define BSP_GPS_ACQ_BASE 0x10020000UL
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#define BSP_GPS_TRCK0_BASE 0x10021000UL
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#define BSP_GPS_TRCK_STRIDE 0x00001000UL
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@@ -0,0 +1,12 @@
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TARGET := max2771_spi_test
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APP_SRCS := main.c
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BSP_SRCS := init.c uart.c max2771_spi.c
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# Direct builds default to Genesys 2. Board flows override these values.
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BSP_UART_CLOCK_HZ ?= 50000000
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BSP_CLINT_TIMEBASE_HZ ?= 500000
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BSP_MAX2771_INPUT_CLOCK_HZ ?= $(BSP_UART_CLOCK_HZ)
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include ../common/app.mk
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CFLAGS += -DBSP_MAX2771_INPUT_CLOCK_HZ=$(BSP_MAX2771_INPUT_CLOCK_HZ)UL
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@@ -0,0 +1,48 @@
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# MAX2771 SPI Register Test
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This bare-metal application exercises the dedicated MAX2771 three-wire SPI IP
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at `0x10016000`. It does not use or alter the generic PMOD SPI peripheral.
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The test uses the complete default register table from the
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[MAX2771 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/max2771.pdf).
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It writes registers `0x0` through `0xA`, reads each register back immediately,
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then performs a second full read sweep and prints all values. Registers `0x0`
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and `0x9` therefore receive the mandatory reserved-bit values required after
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every MAX2771 power cycle.
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Build directly:
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```bash
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make -C soc/software max2771-spi-test
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```
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Build through a board flow:
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```bash
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make -C targets/fpga/genesys2 software APP=max2771_spi_test
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make -C targets/fpga/vcu118 software APP=max2771_spi_test
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```
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For a fast RAM-loaded Genesys 2 test:
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```bash
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make -C targets/fpga/genesys2 debug-load APP=max2771_spi_test
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make -C targets/fpga/genesys2 uart-listen
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```
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Expected final output is:
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```text
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PASS,MAX2771 defaults programmed and verified
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```
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## EV Kit Connection
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The EV kit already has a MAX32625 PICO MCU connected to `SPI_CLK`, `SPI_CSN`,
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and `SPI_DATA`. Before connecting the FPGA, disconnect that controller or put
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all three MCU pins in high impedance and do not run the EV kit GUI. Two active
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masters on `SPI_DATA` can cause electrical contention.
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Connect `SCLK`, `CSN`, the single bidirectional `SDATA`, and a common ground.
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Power the EV kit according to its own guide. Do not connect the FPGA board's
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PMOD power pin to an independently powered EV kit.
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@@ -0,0 +1,81 @@
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#include <stdint.h>
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#include <stdio.h>
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#include "bsp/max2771_spi.h"
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#include "bsp/soc.h"
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#include "bsp/uart.h"
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/* MAX2771 data sheet Table 2, including the mandatory reserved-bit values. */
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static const uint32_t max2771_default_registers[BSP_MAX2771_REGISTER_COUNT] = {
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0xbea41603u,
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0x20550288u,
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0x0eafa1dcu,
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0x698c0008u,
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0x00c00080u,
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0x08000070u,
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0x08000000u,
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0x010061b2u,
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0x01e0f401u,
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0x00c00002u,
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0x010061b0u
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};
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static int report_error(const char *operation,
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unsigned int address,
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bsp_max2771_status_t status)
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{
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printf("FAIL,%s,reg=0x%x,status=%d\n", operation, address, (int)status);
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bsp_uart_wait_tx_idle();
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return 1;
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}
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int main(void)
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{
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printf("\nMAX2771 dedicated three-wire SPI test\n");
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printf("MMIO,0x%08lx\n", (unsigned long)BSP_MAX2771_SPI_BASE);
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bsp_max2771_status_t status = bsp_max2771_spi_init();
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if (status != BSP_MAX2771_OK) {
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return report_error("init", 0u, status);
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}
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printf("CLOCK,input_hz=%lu,expected_input_hz=%lu,sclk_hz=%lu,half_cycles=%lu,max_hz=%u\n",
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(unsigned long)bsp_max2771_input_clock_hz(),
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(unsigned long)BSP_MAX2771_INPUT_CLOCK_HZ,
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(unsigned long)bsp_max2771_sclk_hz(),
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(unsigned long)bsp_max2771_half_period_cycles(),
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BSP_MAX2771_MAX_SCLK_HZ);
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for (unsigned int address = 0u;
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address < BSP_MAX2771_REGISTER_COUNT;
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++address) {
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status = bsp_max2771_write_verified(
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(uint8_t)address, max2771_default_registers[address]);
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if (status != BSP_MAX2771_OK) {
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return report_error("write_verify", address, status);
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}
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}
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for (unsigned int address = 0u;
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address < BSP_MAX2771_REGISTER_COUNT;
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++address) {
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uint32_t value = 0u;
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status = bsp_max2771_read((uint8_t)address, &value);
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if (status != BSP_MAX2771_OK) {
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return report_error("read", address, status);
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}
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printf("REGISTER,0x%x,0x%08lx\n", address, (unsigned long)value);
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if (value != max2771_default_registers[address]) {
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printf("FAIL,read_verify,reg=0x%x,expected=0x%08lx,actual=0x%08lx\n",
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address,
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(unsigned long)max2771_default_registers[address],
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(unsigned long)value);
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bsp_uart_wait_tx_idle();
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return 1;
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}
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}
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printf("PASS,MAX2771 defaults programmed and verified\n");
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bsp_uart_wait_tx_idle();
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return 0;
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}
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Reference in New Issue
Block a user