max2771 spi liens has been added.

soc/software/max2771_spi_test/Makefile

@@ -0,0 +1,12 @@
+TARGET := max2771_spi_test
+APP_SRCS := main.c
+BSP_SRCS := init.c uart.c max2771_spi.c
+
+# Direct builds default to Genesys 2. Board flows override these values.
+BSP_UART_CLOCK_HZ ?= 50000000
+BSP_CLINT_TIMEBASE_HZ ?= 500000
+BSP_MAX2771_INPUT_CLOCK_HZ ?= $(BSP_UART_CLOCK_HZ)
+
+include ../common/app.mk
+
+CFLAGS += -DBSP_MAX2771_INPUT_CLOCK_HZ=$(BSP_MAX2771_INPUT_CLOCK_HZ)UL

soc/software/max2771_spi_test/README.md

@@ -0,0 +1,48 @@
+# MAX2771 SPI Register Test
+
+This bare-metal application exercises the dedicated MAX2771 three-wire SPI IP
+at `0x10016000`. It does not use or alter the generic PMOD SPI peripheral.
+
+The test uses the complete default register table from the
+[MAX2771 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/max2771.pdf).
+It writes registers `0x0` through `0xA`, reads each register back immediately,
+then performs a second full read sweep and prints all values. Registers `0x0`
+and `0x9` therefore receive the mandatory reserved-bit values required after
+every MAX2771 power cycle.
+
+Build directly:
+
+```bash
+make -C soc/software max2771-spi-test
+```
+
+Build through a board flow:
+
+```bash
+make -C targets/fpga/genesys2 software APP=max2771_spi_test
+make -C targets/fpga/vcu118 software APP=max2771_spi_test
+```
+
+For a fast RAM-loaded Genesys 2 test:
+
+```bash
+make -C targets/fpga/genesys2 debug-load APP=max2771_spi_test
+make -C targets/fpga/genesys2 uart-listen
+```
+
+Expected final output is:
+
+```text
+PASS,MAX2771 defaults programmed and verified
+```
+
+## EV Kit Connection
+
+The EV kit already has a MAX32625 PICO MCU connected to `SPI_CLK`, `SPI_CSN`,
+and `SPI_DATA`. Before connecting the FPGA, disconnect that controller or put
+all three MCU pins in high impedance and do not run the EV kit GUI. Two active
+masters on `SPI_DATA` can cause electrical contention.
+
+Connect `SCLK`, `CSN`, the single bidirectional `SDATA`, and a common ground.
+Power the EV kit according to its own guide. Do not connect the FPGA board's
+PMOD power pin to an independently powered EV kit.

soc/software/max2771_spi_test/main.c

@@ -0,0 +1,81 @@
+#include <stdint.h>
+#include <stdio.h>
+
+#include "bsp/max2771_spi.h"
+#include "bsp/soc.h"
+#include "bsp/uart.h"
+
+/* MAX2771 data sheet Table 2, including the mandatory reserved-bit values. */
+static const uint32_t max2771_default_registers[BSP_MAX2771_REGISTER_COUNT] = {
+  0xbea41603u,
+  0x20550288u,
+  0x0eafa1dcu,
+  0x698c0008u,
+  0x00c00080u,
+  0x08000070u,
+  0x08000000u,
+  0x010061b2u,
+  0x01e0f401u,
+  0x00c00002u,
+  0x010061b0u
+};
+
+static int report_error(const char *operation,
+                        unsigned int address,
+                        bsp_max2771_status_t status)
+{
+  printf("FAIL,%s,reg=0x%x,status=%d\n", operation, address, (int)status);
+  bsp_uart_wait_tx_idle();
+  return 1;
+}
+
+int main(void)
+{
+  printf("\nMAX2771 dedicated three-wire SPI test\n");
+  printf("MMIO,0x%08lx\n", (unsigned long)BSP_MAX2771_SPI_BASE);
+
+  bsp_max2771_status_t status = bsp_max2771_spi_init();
+  if (status != BSP_MAX2771_OK) {
+    return report_error("init", 0u, status);
+  }
+
+  printf("CLOCK,input_hz=%lu,expected_input_hz=%lu,sclk_hz=%lu,half_cycles=%lu,max_hz=%u\n",
+         (unsigned long)bsp_max2771_input_clock_hz(),
+         (unsigned long)BSP_MAX2771_INPUT_CLOCK_HZ,
+         (unsigned long)bsp_max2771_sclk_hz(),
+         (unsigned long)bsp_max2771_half_period_cycles(),
+         BSP_MAX2771_MAX_SCLK_HZ);
+
+  for (unsigned int address = 0u;
+       address < BSP_MAX2771_REGISTER_COUNT;
+       ++address) {
+    status = bsp_max2771_write_verified(
+        (uint8_t)address, max2771_default_registers[address]);
+    if (status != BSP_MAX2771_OK) {
+      return report_error("write_verify", address, status);
+    }
+  }
+
+  for (unsigned int address = 0u;
+       address < BSP_MAX2771_REGISTER_COUNT;
+       ++address) {
+    uint32_t value = 0u;
+    status = bsp_max2771_read((uint8_t)address, &value);
+    if (status != BSP_MAX2771_OK) {
+      return report_error("read", address, status);
+    }
+    printf("REGISTER,0x%x,0x%08lx\n", address, (unsigned long)value);
+    if (value != max2771_default_registers[address]) {
+      printf("FAIL,read_verify,reg=0x%x,expected=0x%08lx,actual=0x%08lx\n",
+             address,
+             (unsigned long)max2771_default_registers[address],
+             (unsigned long)value);
+      bsp_uart_wait_tx_idle();
+      return 1;
+    }
+  }
+
+  printf("PASS,MAX2771 defaults programmed and verified\n");
+  bsp_uart_wait_tx_idle();
+  return 0;
+}