onur
af7c43b2a8
The Ti375 fanout could not be resolved with three routing layers, so L5 stops being a dedicated 1.8-V plane and becomes a signal layer. No rail owns a whole layer any more: the supplies are split into zone islands on L4 and L6, L2 and L7 stay solid and completely unrouted, and F.Cu, L3, L5 and B.Cu are all available for signals. Routing is staged rather than handed to the autorouter wholesale. The BGA escape, the buck high-current loops, plane stitching and the local power completion all run first and are locked; Freerouting then sees only the ordinary digital classes, with everything else present as fixed copper. finalize_routing.py installs the audited RF and USB geometry and closes whatever the autorouter left. Four bugs behind the routing failures, all of them the same shape - a layer list written down instead of read from the board, which was correct while L5 was a plane and silently wrong afterwards: - export_routing_stage.py emitted via keepouts for three layers only, so every existing via was invisible to the router on L5. It drove traces straight through them: 102 shorting_items in DRC. - route_local_power.py never used L5 at all, and picked up escape vias on two layers instead of all four. - add_rf_ground() judged fence positions against vias and pads but not tracks. It runs after the session import, when that region already has routed copper, and dropped a ground via on top of a signal trace. route_local_power.py also grew a via cloud on every rail: reaching a plane counted as progress even when it merged nothing, so the same pad collected a via per pass, 0.4 mm further out each time. Progress is now measured by the group count actually falling, and groups already sitting on their plane are skipped. That removed 404 redundant vias. The MAX2771 PLL loop filter was spread across three corners of the package, which forced the charge-pump node onto an inner layer under the GPS front end. All three parts now sit in the pocket at U21's north-west corner and the net stays on F.Cu. A permanent RF_NO_DIGITAL area plus a scoped rule keeps that region free of non-power copper on L3/L5/L6/B.Cu, and the local router enforces the same restriction, since it is the one stage that runs after the temporary keepout is deleted. Also enables the solder-mask bridge check that was switched off board-wide; the board passes it with no violations. Final board: DRC clean - no shorts, clearance, disallowed-item or dangling-copper violations - with 26 unconnected endpoints left. Routing is spread 37% L3, 27% F.Cu, 26% L5, 10% B.Cu over 6548 mm and 971 vias. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
66 lines
3.3 KiB
Plaintext
66 lines
3.3 KiB
Plaintext
(version 1)
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# The edge-launch SMA copper must reach the routed board edge by construction.
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(rule "J2 edge-launch lands"
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(condition "A.Reference == 'J2' || B.Reference == 'J2'")
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(constraint edge_clearance (min -0.01mm)))
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# The manufacturer USB-C locating holes are 0.194 mm from grounded shell
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# lands. This exception is internal to the qualified connector footprint.
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(rule "USB-C locating-hole clearance"
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(condition "A.Reference == 'J1' && B.Reference == 'J1'")
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(constraint hole_clearance (min 0.19mm)))
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# RZV0024A is an ultra-dense high-current package. Its adjusted corner lands
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# and thermal zones meet the selected JLCPCB 0.10-mm copper rule.
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(rule "TPS6287B RZV internal clearance"
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(condition "A.Reference == 'U13' && B.Reference == 'U13'")
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(constraint clearance (min 0.10mm)))
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# Inside the Ti375 escape field the 0.8-mm ball pitch fixes the geometry: a
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# 0.45-mm dogbone via between four lands leaves 0.1407 mm, and a 0.12-mm trace
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# threading between two lands leaves 0.14 mm only if it stays exactly centred.
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# This field therefore runs at the fabricator's 0.10-mm copper minimum, which
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# is what the Default class uses across the rest of the board anyway. The rule
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# only fires when one of the two objects belongs to U1, so it relaxes copper
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# against the balls and nothing else: two tracks crossing the field still owe
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# each other their own net classes' clearance, CLOCK's 0.15 mm included.
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(rule "Ti375 0.8-mm BGA escape clearance"
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(condition "A.Reference == 'U1' || B.Reference == 'U1'")
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(constraint clearance (min 0.10mm)))
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# JLC08161H-3313 L1/L2 geometry. Net-class widths are routing defaults only;
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# these rules make the controlled-impedance geometries actual DRC limits.
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(rule "GNSS 50-ohm CPWG geometry"
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(condition "A.NetClass == 'RF50_CPWG'")
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(constraint track_width (min 0.164mm) (opt 0.164mm) (max 0.164mm)))
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(rule "GNSS RF stays on top layer"
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(condition "A.NetClass == 'RF50_CPWG' && A.Type == 'Track' && A.Layer != 'F.Cu'")
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(constraint disallow track))
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(rule "USB2 90-ohm differential geometry"
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(condition "A.NetClass == 'USB90_DIFF'")
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(constraint track_width (min 0.135mm) (opt 0.135mm) (max 0.135mm)))
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# The TPD2EUSB30A clamp is a SOT-23 whose ground pad sits between its two
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# channel pads, so the pair has to open up for about 1.5 mm to pass it. The
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# 0.90-mm coupled limit still applies over the whole rest of the run.
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(rule "USB2 coupled gap"
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(condition "A.NetClass == 'USB90_DIFF' && AB.isCoupledDiffPair() && !A.intersectsArea('USB_ESD_BREAKOUT')")
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(constraint diff_pair_gap (min 0.15mm) (opt 0.15mm) (max 0.90mm)))
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# The GPS front end owns its region on every layer under F.Cu, so no digital
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# route can run beneath or immediately beside the 50-ohm line and no return
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# path there is broken. Ground stitching and the MAX2771's own supply drops
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# still have to reach it, so the disallow is scoped to the signal classes
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# rather than made a plain keepout. The RF line itself is on F.Cu, which the
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# area does not cover, and L2/L7 stay solid because nothing routes on them.
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(rule "No digital copper under the GNSS front end"
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(condition "A.intersectsArea('RF_NO_DIGITAL') && A.NetClass != 'POWER'")
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(constraint disallow track via))
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(rule "Clock trunk width outside Ti375 escape"
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(condition "A.NetClass == 'CLOCK' && A.Type == 'Track' && !A.insideCourtyard('U1')")
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(constraint track_width (min 0.15mm)))
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